In case you missed it.

Connectors

"Development of Cleanliness Specification for Single-Mode Connectors"

Authors: Tatiana Berdinskikh, Ph.D., Celestica, et al.

Abstract: This paper summarizes research performed by the iNEMI Fiber Optic Signal Performance Project team on development of a cleanliness specification for single-mode connectors. The influence of two grades of Arizona road dust on optical performance of single-mode fibers is investigated. The researchers record insertion loss, return loss and fiber optic microscope images for each connector pair before and after contamination. Interferometry data including radius of curvature, apex offset and fiber undercut are also recorded for each test and reference connector. The changes of insertion loss and return loss as a function of distance of the closest particle from the core are investigated. Results of mathematical modeling of contaminated fibers are correlated with experimental data. The results show that contamination particles can prevent direct physical contact creating an air gap between two endfaces. The area encompassed by a 25 [micro]m diameter from the core is identified as critical. Particles located in this area, even if not directly on the core, result in an increase in insertion loss (a delta of 0.5 to 1.8 dB) and an increase in reflectance (a delta of 10 to 44 dB). Dust particles of 1 to 25 [micro]m result in an air gap of up to 200 nm. (Apex, February 2005)

Packaging

"Utilizing 3-D Package Technology for Complex SiP Applications--Innovative Solutions for System Level Integration and Miniaturization"

Author: Vern Solberg, Tessera Inc.; [e-mail].

Abstract: More functionality typically requires additional or more complex electronics and greater memory capacity. Increasing functional capability, however, can adversely impact the products size as well as manufacturing cost. The challenge manufactures face is to offer a product that will meet all performance and functionality expectations within budget and without increasing product size. This paper explores a number of system level applications developed within Tessera's Package Engineering Service Laboratories, examines results of extensive computer modeling and reviews electrical performance and physical stress testing data. (Apex, February 2005)

Rework

"The Use of SAC Solder and Pb-Free Materials in the Repair Scenario"

Authors: Mark Woolley and Jae Choi, Avaya Inc.; [e-mail].

Abstract: Although the use of lead is limited in new products and equipment, older Pb-containing materials can continue to be used for repair of existing systems. As time progresses, these older Pb-containing materials will need to be repaired using Pb-free components and solders. This study examines repair procedures using a SnAg3.5Cu0.5 alloy and includes bond pull strength tests and cross-sections. (Apex, February 2005)

Solder Joint Reliability

"Design, Materials and Assembly Process of High-Density Packages with a Low-Temperature Lead-Free Solder (SnBiAg)"

Authors: Jerry Gleason, Valeska Schroeder and Gregory Henshall, Hewlett-Packard; John Lau and Walter Dauksher, Agilent; Bob Sullivan, High Density Packaging Users Group.

Abstract: The High Density Packaging Users Group Consortium (HDPUG) has conducted a study of process development and solder joint reliability of high-density packages on printed circuit boards using a low melting temperature lead-free solder (SnBi57 Ag1.0). The design, materials and assembly process aspects of the project are discussed. The components studied include several SMT package types and various lead configurations. The assembly process, addresses the low-temperature lead-free assembly process, inspection and analysis of these boards and packages. (Apex, February 2005)

"Reliability of CCGA and PBGA Assemblies"

Author: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratories; [e-mail].

Abstract: Very limited data are available for thermal cycling behavior of ceramic packages commonly used for aerospace applications. Thermal cycles and vibration test results for ceramic ball grid array (CBGA) with 361 and 625 I/Os were reported previously by this author and the trends for cycles-to-failures for four different temperature ranges were established. This paper presents thermal cycle test results for a ceramic column grid array (CCGA) and its PBGA version, both having 560 I/Os, exposed to two different thermal cycle regimes. One of the thermal cycles was that specified by IPC-9701; i.e., -55 to 125[degrees]C; the other was in the range of -50 to 75[degrees]C representing the qualification for the specific mission. Per IPC-9701, test vehicles were built using daisy chain packages and were continuously monitored. The effects of many processing and assembly variables, including corner staking (commonly used for improving resistance to mechanical loading such as drop and vibration loads), were also considered as part of the DoE test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. A representative sample, along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy to determine crack propagation and failure analyses for packages with and without corner staking, are also presented. (Apex, February 2005)

CIRCUITS ASSEMBLY provides abstracts of papers from recent industry conferences and company white papers. With the amount of information increasing, our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.