Implementing serial ATA in next-generation computer systems.

The Parallel AT Attachment (ATA) storage interface, the longtime industry standard for connecting storage devices to the PC motherboard, is rapidly headed toward obsolescence. Hampered by inherent voltage, pin-count, and performance limitations, Parallel ATA will give way, over the next two to three years, to a new connectivity standard proposed by the Serial ATA Working Group. Formed in early 2000 to develop the specification tot a scalable, serial interface to replace Parallel ATA while maintaining cost parity, the group now comprises more than 70 makers of PCs, drives, chipsets, and related products.

In August 2001, the working group published Draft 1.0 of the Serial ATA specification, which will increase the bandwidth to and from disk drives--ranging from hard drives to CD-RW drives--and other PC components. The new specification will help minimize the increasingly frequent traffic jams that occur inside computers as disk drives struggle to yield the quantity of data required by PCs with 1.4GHz or faster processors. This interface will provide a number of advantages, as well as a performance roadmap for future generations.

Key Benefits of Serial ATA

Ultra ATA/100 and ATA/133, the current Parallel ATA interfaces, offer peak transfer rates of only 100MB/sec and 133MB/sec, respectively. By comparison, first-generation Serial ATA offers a peak bandwidth of 150MB/sec (1.5Gbps serial transfer). The second and third generations of Serial ATA should offer bandwidth of 300MB/sec and 600MB/sec, respectively. This use of gigabit technology will make Serial ATA viable for at least 10 more years, enabling the interface to better keep up with the data-transfer demands of advanced processors. In addition, its point-to-point architecture enables each device in the system to communicate directly with the host processor via a dedicated link. With Parallel ATA, two devices (master/slave) may share a common connection, so if one connection fails, the whole system goes down. Because no buses are used, Serial ATA not only enables a more reliable and robust system--it brings to the internal realm hot-plugging capability, similar to that enabled by USB and FireWire.

Serial ATA will also eliminate Parallel ATA's large, unwieldy ribbon cables, which impede airflow inside the PC chassis, limiting cooling capability. Serial ATA's narrower cables can be made up to 1 meter in length (approximately 3 ft.), enabling more elaborate routing and helping to create cooler-running PCs. Serial ATA serial signaling will also contribute to enhanced system-design flexibility, offering the possibility of smaller packages that require fewer ground and voltage pins.

Serial ATA also employs significantly lower voltage signaling (250mV) than Parallel ATA, which is based on TTL signaling and requires ICs to tolerate input signals as high as 5V. This particular feature of Serial ATA is critical to the coming generation of deep-submicron (DSM) device geometries--those with 0.18-micron and smaller linewidths that are unable to handle very high voltages. This reduced voltage requirement will allow for ease of technology migration, as well as lessen power consumption in conjunction with the reduction in voltage drivers and quantity of signaling pins.

Two key features will allow migration of Serial ATA as the new standard to occur more quickly and easily than with most proposed new interfaces 1) In general, Parallel and Serial ATA possess compatible BIOSes; and 2) the test infrastructure can be supported with bridge devices. Both of these concepts ale explored later in this article.

Serial ATA Design Approach

Serial ATA poses several challenges to system implementers due to changes in the construct not utilized in Parallel ATA. One must bear these in mind when looking at the interface specification. In building a Serial ATA controller, the designer can choose from many architectures and implementations. One possible methodology is described below, to illustrate some of the key issues associated with Serial ATA system design.

Host-side block development

The first thing that should be determined is the interface attachment of the host to the Serial ATA controller. This interface should convert the specifics of that bus to something that directly communicates with the Transport layer of the SATA specification. A design should have an interface block that converts the host interface to hardware to be handled by the Transport layer. Typically, a Transport block will include a Register File that provides a Task File for BIOS register compatibility, to ensure that software drivers are compatible with Parallel ATA systems.

The other major type of hardware block in the Transport block is the Transport layer State Machine, which is responsible for making the interface look like Parallel ATA. This block is responsible for managing the Task File and putting the register-level commands in a format that can be used by the Link layer for further processing. In creating bus-to-protocol bridging, the designer will need to convert his/her bus to match the Task File register-set functionality of the Parallel ATA interface. If this Task File mapping is not achieved, special drivers will be required, and BIOS compatibility--a key goal--will be forfeited.

Once handshaking with these registers has been completed, the designer will need to develop a specialized state machine to handle the Task File and Status operations and make them appear compatible with standard ATA. This state machine will take new commands loaded and interpret their functionality, providing instant status handling at the user interface. The state machine will control the loading and updating of this status register and will also control the operation of the interrupts back to the host.

A host interface block performs the interlace signaling, while the state machine handling the Task File operations is located in the Transport layer State Machine. The transport hardware will hand off the command to the Link layer control block by constructing specialized information blocks to be passed to the Link layer for further processing. The Link block then takes these information blocks and generates the transmit sequence for the Frame Information Structure (FIS), utilizing a specialized Link state machine. The state machine will generate the Align and synchronization data, as well as frame the data to fit into this structure. The sequencer will also enable the CRC hardware to activate and send the data at the appropriate time.

The Link layer is responsible for handling the framing structure of the Serial ATA interface. It provides the header information and 8-bit/10-bit encoding/decoding, along with cyclic redundancy check (CRC) and scrambling. This block is responsible for flow control on the serial interface. The data bytes to be sent out will need to be scrambled, then converted, through an 8B10B encoder, from an 8-bit to a 10-bit data stream, which is then handed to the specialized physical interface hardware block, or PHY. The PHY block takes the encoded data stream and sends it at the high-speed serial data rate (1.5Gbps) called out in the Serial ATA specification. (Note that if the transmission fails, the Link state machine will automatically retransmit the FIS.) The PHY block converts the encoded 10-bit parallel data to serial data, both for sending and for reconverting the received serial stream to a parallel 10-bit value that is handed to the Link layer for decoding back to the 8-bit code and descrambled. This functionality is referred to as SerDes (for Serializer/Deserializer).

The PHY poses the most critical design challenge associated with Serial ATA system design, in that it requires a stable high-speed phase-locked loop (PLL) with very little jitter. This can prove quite challenging in a noisy digital environment. The PHY is also responsible for detecting out-of-band (OOB) interface conditions that allow for OOB signaling sequences for power-on initialization and sleep-mode recovery.

Device-side block development

The preceding paragraphs describe the flow through the key blocks for sending from a host side device. The device side has the same blocks with slight differences. The PHY sends and receives the same encoded data, with a 1.5Gbps differential serial in and a corresponding differential out, fed from the 10-bit parallel-in and 10-bit parallel-out of the PHY. The Link layer takes the frame information and sets the alignment to recognize the start of a frame. From this data, it converts the incoming frame to the traditional ATA format and passes it to the Transport layer. The Transport layer takes this information and loads it into the appropriate outbound register set, which should be a Task File if ATA compatibility is to be maintained. The Transport layer would then write to the device to take appropriate action.

Handshakes back and forth occur in both directions, in much the same way as previously described, with one device block sending information on one serial channel and the other sending information on the other channel. This is often referred to as the forward channel from host to device and the back channel from device to host. The two serial channels use special handshake protocols in getting information back and forth. These special handshakes allow for interlock, allowing each to know what the other side is doing, to prevent information loss and provide mechanisms for returning to a functional state from an error condition.

Because the information flow is occurring at 1.5Gbps, it is not always possible for the Link state machines to keep up when using a bridge device. For this reason, the Link layers must incorporate FIFO buffering to allow for throttling the interface if one side gets behind. This is referred to as flow control, and it allows the link layers to suspend information transmission until the other side is ready. The Serial ATA specification calls out a minimum requirement for the FIFO based on transaction turnaround time. For compatibility and performance reasons, deeper FIFOs are recommended, as some vendors may have excess overhead, creating a potential compatibility issue. Adding extra FIFO depth can help avoid some interface turnaround problems. The depth of the FIFO is key in allowing maximum throughput on the host interface. With a deep enough FIFO, burst transfers at the Transport layer can be better handled.

It's important to note that status updating within the transport block must be handled with care, as the status is generated by the host side in response to a command and is later updated by an FIS on the back channel from a device. The mechanism for accomplishing this is time-critical and must be performed carefully, as should interrupt handling. The figure shows a typical system using the blocks described above.

Bridge vs. Native Devices

Both native and bridge devices are discussed in the Serial ATA specification. Bridge devices enable adaptation of a Parallel ATA host to a Serial ATA interface, or of a Serial ATA interface to a Parallel ATA device, allowing early deployment of Serial ATA in Parallel ATA boards or devices. A native Serial ATA host or device does not perform the Parallel/Serial adaptation, but will directly interface with system buses or the internal logic of a disk controller. Native devices allow maximum throughput, bypassing the legacy Task File reads and writes, as well as the limitation of 133MB/sec for Ultra-DMA Mode 6 transfers to enable the maximum 150MB/sec transfer rate for first-generation Serial ATA products.

There are a number of differences between bridge and native device implementations including:

* DRQ block size. The maximum size in a Data FIS for a native device is 8192 bytes, or 16 sectors, while a Data Request (DRQ) block can have up to 128 sectors. In a native Serial ATA hard disk, the maximum DRQ block must not exceed 16 sectors. In a Serial ATA hard disk with a bridge, the hard disk may report a maximum size of 128 sectors. In this case, if the BIOS/driver does not set the DRQ block to 16 or fewer sectors, the Data FIS can have more than 8192 bytes of data. A similar situation happens in the case of packet programmed fiE) (PIO) commands.

* Support of FISes not used in Parallel ATA environment. FIS types such as BIST Activate and DMA Setup are not used in a Parallel ATA environment. No pins are defined in the Parallel ATA interface for such operations.

* Race conditions between FISes from both sides. In particular, the Serial ATA hard disk may send a Register FIS to the host at the same time when a command is written. It can potentially cause the Register FIS to be interpreted as the response to the newly written command. In a bridge host, this situation is difficult to resolve.

* Serial ATA vs. Parallel ATA power-management states. A bridge device may not automatically know the current power-management state of a parallel ATA hard disk, which can result in additional power consumption. By contrast, the Serial ATA interface can remain on while the device is powered down. There are many such detailed operations that need special attention in a bridge device, as opposed to a native device, where additional signals are available to operate.

Serial ATA Implementation Challenges

As with any new standard, the greatest obstacle to widespread industry implementation of Serial ATA is the communication and functionality issues that must be resolved among various industry players in order to create a true plug-and-play environment. This includes drive manufacturers, motherboard and PC providers, and, especially, chipmakers, as silicon is one of the key gating factors to ramping up Serial ATA. Transitioning to Serial ATA may not be attractive to PC makers until chipset makers have integrated Serial ATA into their silicon. The good news is that virtually all chipmakers have roadmaps leading to Serial ATA products. To ensure these compatibility issues are worked out, Serial ATA adoption will be phased in over the next couple of years, during which time Serial and Parallel ATA will coexist in the PC market.

Another challenge involves the ability to do high-speed serial data transfer. Chip manufacturers that try to force-fit this capability into their silicon will take a yield hit because high-speed serial chips may not yield well. As a result, a trend appears to be developing whereby the logic layers (Link and Transport) will go into chipsets, requiring a separate PHY chip to connect with the logic side. This presents a significant market opportunity for companies that offer a host-side PHY and can facilitate Serial ATA integration on the host side.

ATA has been around for many years, and consumers have become used to being able to buy a drive from any vendor and have it work. Ultimately, Serial ATA will provide this benefit, as well as the many others previously discussed, but this will come only after extensive testing of devices before being introduced to the market.

Initially, Serial ATA will struggle to achieve price parity with Parallel ATA, but this will quickly change as second-generation speeds occur. Major and far more costly changes would be required for Parallel ATA to match Serial ATA in meeting second-generation speeds. The bridge products that provide attachment, at both the host and device sides, will supply a method for initial development and launch of products. They will also enable a cost-effective, software-compatible migration path, greatly reducing the investments and problems associated with new interface support.

While Serial ATA features more complexity than past interface solutions and increases the difficulty of building PHY layers, its benefits outweigh these initial disadvantages for designers. Not only does Serial ATA offer lower pin count, longer, narrower cables, and reduced power for an overall superior solution--it offers a technology-usage and performance roadmap that extends well into the future.

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Bob Norman is the director of strategic marketing and Frank Lee is the director of Storage Products at Silicon Image (Sunnyvale, CA).