INFINEON ANNOUNCES FIRST SINGLE CHIP 40G FRAMER-MAPPER.

Infineon Technologies (FSE:IFX) (NYSE:IFX), has launched the world's first single chip 40G framer-mapper/quad STS-192 device, for next generation synchronous optical networking/synchronous digital hierarchy (SONET/SDH) communication systems. Together with Infineon's recently announced STS-768 MUX/DEMUX chipset, the 40G framer-mapper, offers high-level integration and feature rich functionality to address high-density line card applications for the 10G and emerging 40G markets. With this solution, optical transport system manufacturers can significantly reduce costs and shorten their time-to-market.

"Our goal is to provide customers with the best technologies for today's advanced STS-192 line-card market while giving them the option to migrate to STS-768 as the market evolves," said Jack Basi, vice president of marketing for Infineon's WAN Business Unit. "Infineon's 40G framer-mapper solution, developed by recently acquired Catamaran Communications, will enable makers of high-speed transmission systems to swiftly implement next generation equipment such as Dense Wave Division Multiplexers, Add Drop Multiplexers and Digital Cross Connects in the long haul and metro areas where higher bandwidth, lower power and real estate savings from smaller footprint are the key to success."

The steadily increasing demand for Internet and multimedia data is set to galvanize telecommunications carriers to deploy 40G transmission technologies that require vastly improved performance from ICs. According to Gartner Dataquest (Fiber Optic Food Chain, March 2001), the annual worldwide market for OC-192 and OC-768 framers is set to grow from US$79 million in 2000 to US$2 billion in 2004.

The framer chip announced recently is part of Infineon's overall strategy to offer customers a complete line card solution in the 10G and 40G space from the optical to the network processor interface. Fabricated in a leading edge 0.15 micron process, the framer-mapper is a highly integrated device that provides section, line and path overhead processing as well as frame synchronous scrambling and de-scrambling for quad STS-192. It supports pointer processing at STS-1 granularity for STS-192 and scalable concatenation levels STS-3c to STS-192c for a seamless upgrade path to STS-768 and provides extensive performance, error and alarming functions. Furthermore, it meets all relevant SONET/SDH standards.

Samples of the single chip 40G framer-mapper/quad STS-192 device and evaluation boards will be available in Q4 2001 with mass production scheduled for the first half of 2002.