IEEE Announces Open Meeting on Plans For VHDL-200X At the Design Automation Conference; Meeting to Discuss Enhancements to the Standard for the Popular VHDL Design Language.

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Design Automation Conference 2003

PISCATAWAY, N.J.--(BUSINESS WIRE)--May 22, 2003

The Institute of Electrical and Electronics Engineers (IEEE) has announced that its VHDL Analysis and Standardization Group (VASG) will hold a public meeting for the electronic design and verification community to discuss planned enhancements to the widely used VHDL (Very High-Speed IC Hardware Description Language) standard.

The meeting will be held during the Design Automation Conference (DAC) on June 4 at 6:30 p.m. at the Anaheim (Calif.) Convention Center.

During the meeting, members of VASG, also called the IEEE 1076 (TM) Working Group, will communicate the status and plans for the overall language enhancement initiative, as well as the activities of the specific teams within the group, which are organized along functional and language design lines.

"Given the interests of the VHDL user community, our efforts to revise the IEEE 1076 standard encompass major functional areas, such as design and verification engineer productivity, tool performance, assertion-based verification, and the simulation environment," says Stephen Bailey, IEEE 1076 Working Group chair. "We've set up the meeting at DAC to gain feedback on the work we've done on the language so far and what we intend to do as we complete the upgraded standard."

In anticipating the response from the user community to VHDL-200x, Jim Lewis, President at SynthWorks, says, "I see VHDL-200x as an upward-compatible, evolutionary update crafted with VHDL users in mind. It will build on existing, high-level constructs and add new features and APIs to VHDL."

"These features, which will be similar to those in HVLs (hardware verification languages), will make VHDL a powerful hardware design and verification language. While VHDL-200x will provide interfaces to other languages such as C, the enhancements will make separate HVLs unnecessary for VHDL verification engineers."

The functional teams working on VHDL-200x within VASG are:

-- The Fast Track team, which seeks to gain quick resolution on

issues involving coordination with ancillary standards,

especially the multi-valued logic standard (IEEE 1164, aka

standard logic) and the synthesis packages standard (IEEE

1076.3) now being updated. This team will also evaluate other

enhancement requests for quick adoption, e.g., the ability to

probe and drive internal design signals from the test bench.

-- The Performance team, which is identifying language changes

that allow improved design tools performance, particularly of

simulators, to reduce overall design and verification time.

-- The Assertions team, which is evaluating assertion-based

verification (ABV) languages and capabilities, such as the

proposed Property Specification Language, to determine how

best to provide the benefits of ABV to VHDL users.

-- The Modeling and Productivity team, which is working to make

the designer's life easier by identifying capabilities to make

it easier to model functionality and to reduce the amount of

code needed to model functionality common to digital designs.

-- The Testbench and Verification team, which is addressing

language enhancements for the verification engineer, including

improved support for modeling the environment of a design

under verification and for generating and managing stimuli and

trace information.

-- The Environment team, which is reviewing the operating

environment for design tools, such as simulation control

language and library management, and identifying capabilities

to be incorporated into the standard to ease design

portability.

-- The Data Types and Abstractions team, which is a

specialist-language design team focused on the VHDL type

system. It supports other functional teams and works to add

object-oriented extensions and interface abstractions to VHDL.

-- The Asynchronous Design team, which is addressing modeling and

productivity needs from the perspective of asynchronous design

modeling.

Nearly all work in defining the VHDL Programming Interface (C language application programming interface) has been completed and is awaiting standardization and official inclusion in the VHDL Language Reference Manual. Given this timing, it will be included in the standard for VHDL-200x.

The IEEE 1076 standard, "VHDL Language Reference Manual," is sponsored by the IEEE Computer Society. For more information on VHDL-200x see: http://www.eda.org/vhdl-200x. For more information on DAC see: http://www.dac.com.

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