IDT extends leadership with industry's first 512Kx36, 18-Mbit network search engine with dual LA-1 interfaces.

IDT a communications IC company and the market and technology leader of network search engines (NSEs), has introduced the industry's first monolithic NSEs in 512Kx36 (18-Mbit) and 256Kx36 (9-Mbit) configurations with dual Network Processor Forum (NPF) Look Aside (LA-1) interfaces. The fully integrated interfaces allow a seamless connection between the new IDT NSEs and the network processing units (NPUs), including the nP3700 NPUs from AMCC and the Intel IXP2400, Intel IXP2800, and Intel IXP2850 NPUs. Targeted at metro and edge routers, the new IDT NSEs operate at up to 250 million searches per second (MSPS) and enable line rate performance up to OC-192 and beyond. IDT will discuss technical product details during the Search Engine Panel on Thursday, October 23 at 8:30 a.m. at the Network Processors Conference West, San Jose, Calif.

"To obtain system flexibility in metro and edge routers, designers want search engines that connect glue-lessly with multiple NPUs," said Jag Bolaria, senior analyst at The Linley Group. "Offering a high-density, high-performance search engine with multiple ports further satisfies the classification requirements of multiple OC-192 data paths."

The dual LA-1 interfaces on the new IDT NSEs enable the sharing of databases between ingress and egress NPUs. This feature, coupled with the 18-Mbit density of the 512Kx36 NSE, enables multiple database support for a variety of applications related to multi-field complex classification. The flexibility delivered by the NSE's shared-database capability eliminates the need for multiple updates for rule sets within multiple NPUs, increasing overall performance and system efficiency.

In addition to incorporating two LA-1-compliant interfaces, the new IDT NSEs include a control plane maintenance port with a PCI interface. This port enables efficient table management by allowing users to make changes in the databases without impacting search performance. The NSEs also perform instruction result notification that provides efficient device operation and minimizes the number of transactions required to obtain the search results. Similar to existing devices within the IDT portfolio, the NSEs with dual LA-1 interfaces offer application-support features, such as dynamic database management for increased power savings, and simultaneous multi-database lookup (SMDL) that enables multiple packet searches up to 250 million searches per second (MSPS).

"The new IDT NSEs with dual-LA-1 interfaces extend our leadership in providing innovative solutions that incorporate specialized architectures which accelerate packet processing in a variety of applications requiring multi-field complex classification," said Dave Cech, director of marketing for the IDT network search engines. "We have improved on our existing family of NSEs with LA-1 interfaces by adding a second integrated LA-1 interface that connects to leading NPUs from AMCC and Intel, thereby prolonging the life of metro and edge router designs. In addition, we continue to help designers get to market faster and at a lower cost by providing a complete suite of software and hardware development tools."

Continuing its commitment to deliver comprehensive system solutions, IDT offers with its NSEs a design accelerator kit (DAK), consisting of software and hardware development tools. The IDT software development kit (SDK) includes a dual-port system level architecture model (SLAM), a simulation tool, bundled with the IDT BusTracker and PowerTracker system analysis tools that evaluate bus efficiency and power consumption, respectively. Different versions of the SLAM that integrate directly into the NPU software simulation environments for both Intel and AMCC architectures will be available. This suite enables designers to begin software development early in the design process and to fully evaluate and test multiple packet-processing architectures in a pre-hardware environment. IDT will also provide a hardware development kit (HDK) comprised of a suite of tools that can be used in conjunction with the Intel and AMCC NPU development platforms. Together, these tools speed designers' time to market, increase system performance and lower overall development costs.

The IDT 75Kxxxx 512Kx36 and 256Kx36 NSEs with dual LA-1 interfaces are packaged in a 900-ball flip-chip ball grid array (FCBGA) and will sample in Q1CY04. The IDT NSE in a 512Kx36 configuration is expected to be priced individually at $350 in 10,000-unit quantities.