IDT Introduces Enhanced 9-MBIT Asynchronous Dual-Port Family at Industry's Fastest Speeds.Business Editors/High-Tech Writers SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--Oct. 6, 2003 8ns Devices Enable Improved Execution of Sequential Write Operation by Way of Innovative RapidWrite Mode IDT IDT Integrated Device Technology, Inc. (Santa Clara, CA, USA) IDT I Don't Think IDT Identity Theft IDT Interrupt Descriptor Table IDT Integrated DNA Technologies IDT Inactive Duty Training IDT Instructional Design & Technology (TM) (Integrated Device Technology IDT (NASDAQ: IDTI) was founded in 1980 as a semiconductor vendor. Employing approximately 2500 people worldwide, headquartered in San Jose, California and operating a fab in Hillsboro, Oregon, the company both designs and fabricates semiconductor components. , Inc.)(Nasdaq:IDTI IDTI Integrated Device Technology Inc ), a leading communications IC company, today demonstrated its leadership in multi-port technology with the introduction of an enhanced 9-Mbit asynchronous Refers to events that are not synchronized, or coordinated, in time. The following are considered asynchronous operations. The interval between transmitting A and B is not the same as between B and C. The ability to initiate a transmission at either end. dual-port family that offers the fastest access times in the industry. The new 9-Mbit asynchronous dual-port devices operate at access times as low as 8ns, enabling increased performance for the fastest shared memory (1) Using part of main memory to support a low-cost display circuit that does not have its own memory. See shared video memory. (2) The common memory in a symmetric multiprocessing system that is available to all CPUs. See SMP. 1. applications, including wireless base stations, storage area networks and network switches and routers. Unlike alternative solutions, the new products offer an innovative RapidWrite Mode that allows designers to more easily perform sequential write functions - a key capability to ensure optimum write performance at 8ns cycle times. The dual-port devices are pin-compatible with the company's existing 10ns offerings and 4-Mbit asynchronous dual-port products, enabling an easy upgrade path with minimal board changes. Other unique features include a 2.5-volt core for low-power consumption, selectable 2.5- and 3.3-volt I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output options for voltage bus matching between two separate domains, and an innovative sleep mode. "As our customers continue to grapple with to enter into contest with, resolutely and courageously. See also: Grapple the evolving design requirements of the global network, we are constantly evaluating ways in which to anticipate their needs by way of our proven innovation and expertise in multi-port technology," said Bill Beane, strategic marketing manager for the IDT multi-port products division. "These new dual-port devices validate our commitment to solving our customers' complex design challenges. The 8ns access times enable customers to achieve the highest level of asynchronous performance available, while the RapidWrite Mode allows them to take full advantage of this high level of performance during back-to-back write operations such as updating headers or maintaining a pointer structure in the memory." In addition to improved performance, the new IDT family of dual-port products provides several mechanisms designed to enable customers to address contention issues between ports, such as "busy" arbitration logic, semaphore semaphore (sĕm`əfôr'), device for the visible transmission of messages. The marine semaphore, used by day between ships or between a ship and the shore, consists essentially of a post at the top of which are two pivoted arms. flags and interrupts. More specifically, the busy arbitration logic determines which port has control of the specific memory location, grants control to that port, and then outputs a busy flag on the opposite port to indicate a wait signal until the location is available for access. Semaphore flags provide a hardware mechanism that allows the designer to manage the use of system resources (1) In a computer system, system resources are the components that provide its inherent capabilities and contribute to its overall performance. System memory, cache memory, hard disk space, IRQs and DMA channels are examples. , including operations within the shared memory itself. Interrupts provide a specific mailbox location for each port that can be used to enable software to communicate the port status to the opposite port, facilitating inter-port communication and management of the shared resource Sharing a peripheral device (disk, printer, etc.) among several users. For example, a file server and laser printer in a LAN are shared resources. Contrast with shared logic. . The devices' new and unique RapidWrite Mode allows designers to perform consecutive write cycles without pulsing the write, enabling control pins inactive during address and data transitions. The ending address transition then becomes the critical reference point for the write operation termination, facilitating implementation of the fastest consecutive write cycles possible. This device family also provides the industry's largest available asynchronous shared memory size, giving designers the option to eliminate multiple memories in an application, thereby lowering design complexity, board space and cost. The innovative sleep mode feature allows the products to minimize power consumption by placing the part in full standby mode A sleep mode in a portable computer that provides an almost immediate resumption of operation when turned back on. In standby mode, the hard disk and display are turned off, and the CPU is throttled down to its lowest-power state. without any input level restrictions. Other features include a JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group interface, which allows designers to improve manufacturability with enhanced board debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. and production diagnostics, as well as space-saving ball grid array “BGA” redirects here. For other uses, see BGA (disambiguation). A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. packaging. Pricing and Availability Pricing for the 8ns, 9-Mbit, asynchronous dual-port devices starts at $88.15 in 10,000-unit quantities with production quantities currently available. In addition to the 9-Mbit devices, the new family includes 2.5-volt asynchronous parts in 4-Mbit densities. These devices are priced at $67.80 in 10,000-unit quantities, and are also available now in production quantities. More information about these and other multi-port products can be found on the IDT Web site at http://www.idt.com/products/pages/Multi-Ports.html. High-resolution, downloadable photos of the 8ns, 9-Mbit, asynchronous dual-port products are located at http://www10.idt.com:81/pressroom/imagebank/products.cfm .
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70T651S8 8ns 256-ball BGA NOW NOW $88.15
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