IDT Delivers Industry's Highest-Performance Bank-Switchable Dual-Ports at 200 MHz; Enhanced Devices Target High-Speed, Bandwidth-Intensive Communications Applications.Business/High Tech Editors SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--April 15, 2002 IDT IDT Integrated Device Technology, Inc. (Santa Clara, CA, USA) IDT I Don't Think IDT Identity Theft IDT Interrupt Descriptor Table IDT Integrated DNA Technologies IDT Inactive Duty Training IDT Instructional Design & Technology (Integrated Device Technology IDT (NASDAQ: IDTI) was founded in 1980 as a semiconductor vendor. Employing approximately 2500 people worldwide, headquartered in San Jose, California and operating a fab in Hillsboro, Oregon, the company both designs and fabricates semiconductor components. , Inc.) (Nasdaq:IDTI IDTI Integrated Device Technology Inc ), a leading communications IC company, today expanded its industry-leading multi-port product portfolio through the delivery of speed enhancements to its family of bank-switchable dual-ports. With speeds up to 200 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. and up to 9 Mbits of data storage, these dual-ports provide the highest performance and density on the market, supplying the higher bandwidth demanded by communications architectures in the enterprise market, including switches and routers, and storage area network applications. Unlike alternative 9-Mbit dual-port solutions that rely on multiple internal die, IDT delivers these high-density devices in a single die configuration, which results in distinct advantages in performance, functionality, power management, reliability, and cost-per-bit, all of which are critically important in high-bandwidth applications. IDT's new devices offer faster data transfers and improved flexibility to the system designer, while also allowing for additional data storage and reduced system costs. Additionally, IDT's bank-switchable dual-ports' aggressive cost-per-bit allows for lower overall system costs. These devices also offer up to a 30% power reduction on 133MHz speed grades and a 15% power reduction on 166MHz speed grades when compared to previous bank-switchable dual-port iterations. The 36-bit and 18-bit devices feature selectable 3.3-volt/2.5-volt input/output (I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output ) operations, with the 3.3-volt options supporting speeds up to 200 MHz and the 2.5-volt options supporting speeds up to 166 MHz. The flexibility in bus width, voltage, and operating speeds The operating speed of a road is the speed at which motor vehicles generally operate on that road. The precise definition of "operating speed", however, is open to debate. enable designers to interface with families of new network processors and digital signal processors A digital signal processor (DSP) is a specialized microprocessor designed specifically for digital signal processing, generally in real-time computing. Characteristics of typical Digital Signal Processors
"Our 200 MHz bank-switchable devices enable designers to share high-density, high-performance memory resources in multi-processor system environments, while also delivering the flexibility needed to accommodate a wide range of design issues," said Bill Beane, strategic marketing manager for IDT's multi-port products. "Fabricating these devices in volume production has further enabled us to support our customers with the industry's lowest cost-per-bit multi-port solution, providing the superior performance they need at a very competitive system cost." IDT's Bank-Switchable Architecture Simplifies Design Cycle The high-speed bank-switchable dual-ports are organized into 64 banks within a common memory array, surrounded by multiplexing multiplexing, in communication, technique whereby two or more independent messages, or information-bearing signals, are carried by a single common medium, or channel. circuitry to allow each bank to be accessed by either port. The devices are capable of supporting frequencies up to 200 MHz on buses of various widths, frequencies and voltage levels. The dual-ports feature separate, independent clocks In telecommunications networks, independent clocks are free-running precision clocks located at the nodes which are used for synchronization. Variable storage buffers, installed to accommodate variations in transmission delay between nodes, are made large enough to on each port to support communication between buses running at different frequencies, even with the two ports set at different voltage levels. The two ports on the device are able to operate simultaneously, doubling the available bandwidth. The simultaneous access of the dual-port product and its synchronous Refers to events that are synchronized, or coordinated, in time. For example, the interval between transmitting A and B is the same as between B and C, and completing the current operation before the next one is started are considered synchronous operations. Contrast with asynchronous. interface improves performance, while simplifying the design process and speeding time to market. The 200 MHz operating frequency supports high data transfer rates up to 14 Gbps, while the 3.3-volt core operating voltage provides lower power consumption. As the dual-port consumes less board space and is based on an architecture with an aggressive cost-per-bit, designs using dual-port products can be more space- and cost-efficient. Shared network devices will also benefit from the parity bits An extra bit attached to the byte, character or word used to detect errors in transmission. (storage, communications) parity bit - An extra bit added to a byte or word to reveal errors. See parity. that support error detection and correction (algorithm, storage) error detection and correction - (EDAC, or "error checking and correction", ECC) A collection of methods to detect errors in transmitted or stored data and to correct them. This is done in many ways, all of them involving some form of coding. . Pricing and Availability The 200 MHz 9-Mbit bank-switchable devices in 256-ball BGA (Ball Grid Array) A popular surface mount chip package that uses a grid of solder balls as its connectors. Available in plastic and ceramic varieties, BGA is noted for its compact size, high lead count and low inductance, which allows lower voltages to be used. packaging are in full production and shipping today. Additional package options will follow in the third quarter of this year. Pricing starts at $52.99 for 10,000-unit quantities. Additional product information can be found on IDT's Web site at http://www.idt.com/bank_switchable.
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Part Configuration Speed Pin/ Samples Production Price/Qty.
Number Package Quantities (10K Units)
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70V7519 256Kx36 200 MHz 256-ball Now Now $68.90
BGA
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70V7599 128Kx36 200 MHz 256-ball Now May 2002 $60.95
BGA
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70V7589 64Kx36 200 MHz 256-ball Now May 2002 $52.99
BGA
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70V7339 512Kx18 200 MHz 256-ball May 2002 June 2002 $68.90
BGA
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70V7319 256Kx18 200 MHz 256-ball May 2002 June 2002 $60.95
BGA
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70V7399 128Kx18 200 MHz 256-ball May 2002 June 2002 $52.99
BGA
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