IBM Researchers Demonstrate World's Fastest Computer Circuits: Experimental Design Runs at Five Times the Speed of Current Fastest Chips; Could Cut Power Consumption in Half.

Business and Technology Editors

SAN FRANCISCO--(BUSINESS WIRE)--Feb. 7, 2000

IBM Research today announced breakthrough results in developing a new family of experimental high-speed computer circuits that run at test speeds up to five times faster than today's top chips.

The new circuits employ an innovative design -- called &uot;Interlocked Pipelined CMOS&uot; -- to reach speeds of 3.3 - 4.5 billion cycles per second (3.3 - 4.5 GHz) using conventional silicon transistors, while dramatically reducing power consumption. IBM researchers estimate that chips made with IPCMOS circuits would require only half the power used by a standard high-performance chip.

&uot;To meet continuing demand for performance, we're going to have to look beyond simply making circuits smaller,&uot; said Dr. Randall D. Isaac, vice president, Systems, Technology, and Science, IBM Research. &uot;Increasingly, performance gains will be driven by innovations in chip design. With breakthroughs such as our silicon-on-insulator technology moving into the market, and new circuit architectures and promising research like IPCMOS under way in our labs, IBM is building its arsenal for the era of multi-gigahertz chips.&uot;

Speeding Up the Clock

The key to the IPCMOS design is a distributed &uot;clock&uot; function. In computer chips, the clock paces the speed of the circuits. Standard designs use a centralized clock to synchronize the operations of an entire chip, ensuring that all operations run at the same interval, or cycle. The clock waits for all the operations on a chip to finish before starting the next cycle, so the speed of the entire chip is limited to the pace of the slowest operation. To increase the speed, the IBM researchers decentralized the clock, using locally generated clocks to run smaller sections of circuits. This locally generated clock has two significant advantages:

- Speed -- Faster sections of circuits are free to run at higher

cycles without needing to wait for slower operations to catch up.

- Power -- The distributed IPCMOS clocks send signals locally only

when an operation is being performed, significantly reducing

power requirements. Centralized clocks send a signal to the

entire chip, and the synchronizing function can use as much as

2/3 of the total power consumed.

&uot;Maintaining a synchronous clock across an entire chip becomes increasingly difficult as performance rises, and the clock itself can limit performance,&uot; said Stanley Schuster, one of the researchers working on IPCMOS. &uot;We believe this new design will help us overcome those problems in future generations of high-speed chips.&uot;

Conference Highlights

The IPCMOS research will be presented on February 9 at the annual International Solid-State Circuits Conference that opens today in San Francisco. Technology highlights of the 14 IBM papers being presented at ISSCC include:

High-frequency, Short-pipeline Processor -- using copper interconnects, novel circuit design, and dynamic programmable logic arrays to achieve frequencies of 1GHz or more using existing production technology with a short-pipeline architecture.

Embedded DRAM -- demonstration of a unique copper-based embedded DRAM design with density comparable to DRAM and speed comparable to the fastest SRAM. The design could be used in future GHz system-on-a-chip products, and would provide a data-transfer rate of 1 terabit per second.

760 MHz S/390 G6 Microprocessor -- a high-speed complex instruction set chip used in the first commercial server powered by copper interconnect technology, offering 27% frequency improvement over the previous-generation processor.

&uot;Millipede&uot; -- a prototype micromechanical device for high-density storage that would use an array of 1,000 tiny cantilevers to read and write data -- with possible storage densities of over 400 billion bits per square inch (400 Gbit/in2).

MRAM -- an experimental solid-state memory technology that could someday lead to truly non-volatile random access memory with both the high speed of SRAM and the high density of DRAM.

More information about IBM is available through the IBM home page at http://www.ibm.com.