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How to read a roadmap: roadmaps are invaluable but can be misunderstood. A roadmap may claim that microvias are standard technology, for example, but it doesn't mean they are standard for every PCB shop.

Roadmapping is not a new activity. Corporations such as Motorola in the U.S. and Phillips in Europe have decades of experience using roadmaps. Technology roadmaps are mechanisms enabling industry, academia, private researchers and governments to identify the new critical technologies, skills and competencies required to meet future market demands. Typically roadmaps are an accumulation of tables representing how an attribute changes over some time period.

But what do all those tables mean? Do the numbers in the tables represent the OEM's next generation of products or the products where the OEM makes most of its revenue? Do the numbers represent realistic needs for future product development or just a wish list that the OEM has put together, with the ultimate goal of reducing purchasing costs?

In April 2002 PC FAB published an article that discussed some of the differences in national technology roadmaps. (1) That article identified differences in the roadmaps in:

* Team makeup.

* Emulator preparation and data.

* Ramp-up production curve.

This month we add to that discussion one more factor--Focus and Foundation--and review and analyze one table from each of the roadmaps in order to provide a better understanding.

Focus and Foundation

All roadmaps have a focus that is usually stated early in the document. The IPC roadmap's stated focus is "electronic interconnections including the processes and materials for fabrication, plus the attachment mounting of electronic components." (2) Knowing the focus helps the reader to understand the scope of the roadmap, but it doesn't reveal the foundation of the roadmap. The foundation is much harder to determine than the focus. It is not generally stated anywhere in the roadmap discussion. It is often not intentionally planned by the sponsors of the roadmap; rather, it occurs naturally. For example, the silicon industry roadmap, The International Technology Roadmap for Semiconductors, has a research-based foundation. The other two U.S. national technology roadmaps are not as research-based as is the ITRS roadmap. Reason: The semiconductor industry spends approximately 10% of its revenues on R&D. By contrast, the PCB industry spends less than 1% of its revenues on R&D. As such, researchers from government and academia who rely on research dollars to stay in business naturally drift toward the ITRS roadmap.

The foundation of the NEMI roadmaps is based on OEM products. The persons whom most influence the NEMI roadmap are OEM new product planners, not researchers or manufacturing process engineers. At IPC, the greatest influence comes from the manufacturing infrastructure--process engineers, materials engineers and manufacturing management.

It is notable that all three North American roadmaps are influenced most by groups with different backgrounds and each would potentially have a different use for the data. There is nothing faulty about any of these influences; in fact, it may just be the natural order of things. The point is, even at this early stage of comparison the roadmaps are already revealing differences.

Japanese roadmaps add another factor into the equation. U.S. roadmaps are generally "needs" driven: The authors try to determine future product needs and plan the roadmap to satisfy those needs. Japanese roadmaps do this too, but they add a dimension: marketing. Via their roadmaps, the Japanese market their technology leadership. A good example of this is the Japanese Jisso roadmap. In these roadmaps the authors compare Japanese technology with the IPC and SIA roadmaps. There are actually tables that demonstrate this comparison. (Curiously, the Japanese always seem to be slightly ahead.)

To the periodic reader of roadmaps this piece of the foundation is not obvious nor is the information readily available, but it significantly influences the roadmap output.

Understanding Roadmap Tables

IPC. TABLE 1 comes from the chapter on organic product boards in the IPC roadmap. This table describes how phototools need to change to meet technology requirements over the roadmap time flame of 10 years.

There are four rime periods: current, near-, mid- and long-term. Each period is then divided into two columns: RCG, or revenue center of gravity, and SoA, or state of the art. IPC's is the only North American roadmap that differentiates these production classes. (The Japanese Jisso roadmap also uses differentiators.) SoA is defined as technology that the OEM is just bringing to market. It is manufactured in much lower volumes than RCG and is often manufactured on one-of-a-kind or specially modified tools and unique processes that may still require constant monitoring. RCG is defined as technology that the OEM uses to make 85-95% of its revenue. This includes very high volume production, usually available from multiple sources worldwide and produced with tools and processes readily available to industry.

The difficulty with these technology differentiators is that there can still be variation from PCB manufacturer to manufacturer. For example, the roadmap can stare that 150 [micro]m microvias are RCG and 60 [micro]m microvias are SoA and this would be accurate for manufacturers that make microvias. However, for manufacturers that do not make microvias as a regular part of their business, making a 150 [micro]m microvia would be very difficult or impossible. Roadmaps are used for many different reasons and misinterpreting the roadmap data can be a problem. For example, a PCBs buyer might wrongly assume that because the roadmap says that 150 [micro]m microvias are RCG, every PCB shop can produce them at high volume and at minimum cost.

Reading this table further, we can see the attributes that the roadmap authors consider significant for photo-tool requirements. To wit, we see that "Feature Size" RCG needs will shift from 125 [micro]m in 2002 to 75 [micro]m in 2012, a decrease of 50 [micro]m in 10 years. The corresponding SoA requirement will change from 50 [micro]m today to 30 [micro]m in 2012. The other attributes change similarly. Although the 2002 roadmap did not contain a similar table for organic packaging substrates, because of the increased density requirements the needs would be tighter for the same attributes.

TABLE 2 is also from the organic product board chapter and would be interpreted the same as Table 1.

NEMI. TABLE 3 is a portion of a table taken from the 2002 NEMI roadmap optoelectronics chapter. (3) This chapter is a comprehensive review of the status and fixture of optoelectronics technology.

Time periods in the NEMI roadmap are again divided into four segments: 2002, 2005, 2010 and 2015. In this case we can see that the data discuss technology at a much higher level than that of the IPC roadmap. There are two reasons for this. First, the IPC roadmap is an "operational level" roadmap; it provides data at the operation level of PCB manufacturing and assembly. NEMI's roadmap looks at the entire electronics industry and from a higher perspective than IPC's. Second, optoelectronics is still in its infancy and there is not a lot of operational level data available, especially concerning optoelectronic substrates.

Table 3 provides a nice overview of the market drivers, level 2 needs and substrate needs at a high level. Analyzing the substrates row, we see separate electrical PCBs and point-to-point optical in 2002. By 2005 a surface laminated fiber plane emerges, a type of decal that would contain optical fiber and attaches to the PCB surface. The first sign of buried waveguides appears in 2010.

ITRS. TABLE 4 is an excerpt of a very large table in the ITRS roadmap. (4) In this table, we see bali grid array and chipscale package attributes with the corresponding PCB line widths and spaces requirements for escape from under the component. This table shows a significant decrease in solder ball pad pitch, down to a very tight 0.1 mm in 2018. We see a corresponding decrease in line widths and spaces: 12 [micro]m (0.005") lines and spaces will be required to escape from under the components. In April 2002 we discussed the aggressiveness of the ITRS roadmap predictions; this table is a good example.

Jisso. TABLES 5 and 6 are taken from the Jisso roadmap. (5) The Jisso roadmap has been published twice in Japan, with both later translated into English. Table 5 is the production classification used in Japan. It is similar to IPC's but adds one class. Table 6 is the material characteristics that the authors think will be needed for future products.

Looking at some of the attributes we see that in 2010 Tg is expected to rise substantially for all classes. At present Tg is 130[degrees]C for Class A, 165[degrees]C for Class B and 185[degrees]C for Class C. It will rise to 185[degrees]C, 210[degrees]C and 260[degrees]C, respectively, probably because of the higher temperatures of lead-free solders.

In 2010, Class A dielectric characteristics (dielectric constant and dissipation factor) will be the same as the current characteristics (DK: 4.7; dissipation factor: 0.015). For Class B, corresponding to higher frequency of electronics products in which the PCB is used, Dk needs to be reduced from 4.5 at present to 3.0 and dissipation factor from 0.013 to 0.005. For Class C, Dk needs to be reduced from 3.5 to 2.0 and dissipation factor from 0.007 to 0.001. To achieve the requirements of Class C, it will be necessary to develop new resin and reinforcing materials.

We can see that each roadmap looks at technology from a different viewpoint. The differences make it difficult to bridge the documents, but it can be done if one understands each roadmap's purpose and focus and considers that purpose when analyzing the attribute data.
TABLE 1. Phototool Requirements

ATTRIBUTE CURRENT NEAR TERM
 2002-2003 2004-2005

 RCG SoA RCG SoA

Feature Size
 ([micro]m) 125 50 100 45
Feature
 Tolerance
 ([micro]m) [+ or -] 25 [+ or -] 10 [+ or -] 20 [+ or -] 9
Location
 Accuracy
 ([micro]m) [+ or -] 40 [+ or -] 15 [+ or -] 35 [+ or -] 15
PPM [degrees]C 18 14 17 12
PPM %RH 12 8 8 6

ATTRIBUTE MID TERM LONG TERM
 2006-2007 2008-2012

 RCG SoA RCG SoA

Feature Size
 ([micro]m) 80 38 75 30
Feature
 Tolerance
 ([micro]m) [+ or -] 15 [+ or -] 7 [+ or -] 15 [+ or -] 6
Location
 Accuracy
 ([micro]m) [+ or -] 30 [+ or -] 12 [+ or -] 25 [+ or -] 10
PPM [degrees]C 14 10 12 8
PPM %RH 7 5 6 4

RCG: Conventional (practiced by 95% of the industry). SoA: State of the
art (practiced by 5% of the industry). Source: IPC National Technology
Roadmap

TABLE 2. Innerlayer Imaging

ATTRIBUTE CURRENT NEAR TERM MID TERM LONG TERM
 2002-2003 2004-2005 2006-2007 2008-2012

 RCG SoA RCG SoA RCG SoA RCG SoA

Feature Size
 ([micro]m) 125 50 100 45 80 38 75 30
Tolerance
 ([micro]m) 35 10 25 9 20 7 15 5
Defect Size as
 % of Image 20 20 20 20 20 20 20 20

RCG: Conventional (practiced by 95% of the industry). SoA: State of the
art (practiced by 5% of the industry). Source: IPC National Technology
Roadmap

TABLE 3. NEMI Roadmap on Optical Technology

TECHNOLOGY 2002 2005

Market drivers Unchecked network SP OpEx reduction--%
 growth. revenue growth / %
 headcount > 10.
 Service provider
 consolidation. SP ROI improvement,
 cost reduction ~50%.
 Maximize use of
 installed Incremental capex
 infrastructure--0 capex model--capital tied to
 model. each service revenue
 connection.
 Asian market growth.
 Access enablement and
 edge growth.

OE Level 2 Function Long haul: OC48-192 Long haul: OC192-768,
and Application 2.5-10 Gbps. SONET/SDH 10-40 Gbps, 160
 80% (excess capacity), [lambda].
 OEO conversion CDR.
 Metro, access: IP,
 Metro, access: ATM, IP SONET on (C)WDM optical
 on T1/DS3 phy, some phy.
 OCN.
 SAN/LAN, FTT,
 SAN/LAN, last mile: automotive, wireless:
 relatively low volume. 10 GigE, IP (growth
 strongly dependent on
 cost), optical phy and
 10/100/1000 phy
 consumption.

Substrates Separate electrical Surface laminated fiber
 PCBs and point-to-point planes, connector
 optical fiber. terminated. First
 generation optical
 Laminated fiber bundles backplanes (passive
 and harnesses with optical
 connector termination. interconnection).

 Module-module
 (CPU-memory).

TECHNOLOGY 2010 2015

Market drivers Network(s) integration. Protocol
 simplification.
 Seamless scalability.
 Network consolidation.
 Core BW growth ramps.
 Hi-B/W wireless.
 Edge applications grow.

OE Level 2 Function Long haul: 40-160 Gbps, Optical domain packet
and Application AON, [lambda] and bit-level
 provisioning, switching.
 restoration and 10G
 logical layer Solitons--new physical
 management. medium.

 Access: 100 GigE, IP-optical--GMPLS
 (D)WDM, 10/100GBE interworking.
 switches--GbE on
 wireless and optical 40G logical layer mgt.
 phy.
 Phy bridging systems.
 SAN/LAN, FTT,
 automotive, wireless,
 end customer/venue
 media: 10-100 GigE,
 CWDM.

Substrates Embedded optical Standard platform,
 waveguides with integrated OE
 any-point interconnects components and
 (connector and substrates (opto PCB,
 component). PLC, or other).

 Optical backplanes, Edge-to-edge or
 pluggable stackable connectivity.
 daughtercards.

Source: NEMI Roadmaps

TABLE 4. BGA and FBGA/CSP Package PCB Solutions

YEAR OF PRODUCTION 2003 2004 2005 2006 2007 2008

FBGA/CSP solder ball
 pad pitch (mm) 0.4 0.4 0.3 0.3 0.2 0.2
Pad size ([micro]m) 160 160 120 120 80 80
Line width ([micro]m) 48 48 36 36 24 24
Line spacing ([micro]m) 48 48 36 36 24 24
No. rows accessed 3 3 3 3 3 3

YEAR OF PRODUCTION 2009 2012 2015 2018

FBGA/CSP solder ball
 pad pitch (mm) 0.2 0.15 0.15 0.1
Pad size ([micro]m) 80 60 60 40
Line width ([micro]m) 24 18 18 12
Line spacing ([micro]m) 24 18 18 12
No. rows accessed 3 3 3 3

Source: ITRS Roadmap

TABLE 5. Classified Production Technology Difficulties

CLASS REQUIRED PRODUCTION PRODUCTION COST
 TECHNOLOGY RATIO

Class A General technology 80% Reasonable
(conventional)

Class B Advanced technology 15% Cost up
(leading edge)

Class C Most advanced 5% High cost
(state of the art) technology

Source: Jisso Roadmap

TABLE 6. Characteristics of Multilayer PCB Base Materials

ITEM CLASS 2000 2003 2005 2010
Tg ([degrees]C) Class A 130 150 165 185
 Class B 165 185 200 210
 Class C 185 210 230 260
Dk (@t MHz) Class A 4.7 4.7 4.7 4.7
 Class B 4.5 4.5 3.5 3.0
 Class C 3.5 3.5 3.0 2.0
Dielectric Class A 0.015 0.015 0.015 0.015
dissipation factor Class B 0.013 0.010 0.007 0.005
(@1 MHz) Class C 0.007 0.003 0.003 0.001
CTE (ppm/[degrees]C) Class A 16 16 14 14
 Class B 14 14 10 8
 Class C 10 10 9 6
Solder heat tolerance Class A 260/30 260/30 260/30 260/30
(Max.[degrees]/s) Class B 260/180 260/180 260/180 260/180
 Class C 288/180 288/180 288/180 288/180
Copper foil peel Class A 1.6 1.6 1.6 1.6
strength (kN/m) Class B 1.4 1.4 1.3 1.3
 Class C 1.0 1.0 0.5 0.5
Flexural strength Class A 490 490 490 490
(N/[mm.sup.2]) Class B 490 490 490 490
 Class C 550 550 550 550
Modules in flexure Class A 23.5 23.5 23.5 23.5
(GPa) Class B 24.6 27.5 27.5 27.5
 Class C 30 30 30 30
Moisture absorption Class A 0.25 0.20 0.10 0.10
D-25/24 (%) Class B 0.20 0.10 0.08 0.05
 Class C 0.06 0.04 0.03 0.02

Source: Jisso Roadmap


REFERENCES

(1.) Jack Fisher, "Understanding Roadmaps," PC FAB, April 2002.

(2.) IPC, 2002/2003 National Technology Roadmap for Electronic Interconnections, March 2003.

(3.) NEMI, NEMI Technology Roadmaps, December 2002.

(4.) ITRS, International Technology Roadmap for Semiconductors, 2003.

(5.) International Sematech, Japan Jisso Technology Roadmap, 2001.

JACK FISHER is founder of Interconnect Technology Consultants and a member of the PCD&M Editorial Review Board. He can be reached at 512-930 5666; fish5er@mindspring.com.
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Title Annotation:Technology Forecasting
Author:Fisher, Jack
Publication:Printed Circuit Design & Manufacture
Date:Mar 1, 2004
Words:2636
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