High-speed: PCB design basics: consistency in impedance requires cooperation and coordination between the designer and the fabricator to optimize success.

The signaling speed of ICs on PCBs is getting faster. If your company is not currently designing high-speed boards, it probably will soon. Some manufacturers have been shrinking die parts, making the edge rates of signals faster. Other manufacturers will take the opportunity to change the die at the same time they make the parts RoHS compliant. Parts that have always worked in a design may not work properly at the new higher speeds. Additionally, boards will need to be designed with more care and more constraints. This article will focus on some basic ways to incorporate high-speed characteristics into board design, leaving the in-depth electrical information about why they should be done that way for another time.

There are many goals of high-speed designing. Designers must know characteristics that are needed on the parts that are used. They will also need to understand transmission lines and how signals will flow on the board. It is important to know how to control impedance of those signals and the reflections that result from mismatches. As rise times shorten, it becomes vitally important to know how to achieve and maintain good signal integrity, including crosstalk, reflections, termination, placement and routing. Also, designers must know and understand power distribution and decoupling strategies that will allow the board to function properly.

Choosing the right parts

The fastest signals create the greatest possibility for signal integrity problems. Therefore it is important to choose the slowest parts that will do the job properly. There are fewer issues with slower parts and they offer more control than faster parts.

Some parts will route better than others in a group. Differences in the pin-out or overall shape of parts can cause less than desirable routing scenarios affecting the integrity. If the board designer foresees difficulty in routing a particular footprint, it is probably a good idea to discuss this with the circuit designer and ask for a different part that will provide the same function and fit into the whole routing scheme.

The power and ground pins of a part are important too. If a BGA has all the power and/or ground balls in the center of the part, there is a longer return loop for the signals away from that area. This can result in increased crosstalk and EMI problems. Additionally, if the parts used have their power and ground pins far apart, as with Dip packages, there is increased inductance and return loop problems. It is best to use parts that have these pins right next to each other.

Lead frame inductance should also be considered. Generally, the larger the part, the more lead frame inductance there is. The inductance can come from several sources, such as the length of wire from the die to the pin, the type of leads on the part or the size of the pads of a large capacitor as compared to a smaller one.

Flow of Signals

In order to design high-speed boards signal flows must be understood. Basically, when a current flows in a trace, there is an equal and opposite return current flowing in nearby copper. The return current flows whether we design a place for it to go or not, so it is best to always design that place by having a plane adjacent to the signal layer. The basic definition of a transmission line is a signal and its return path, and the return current defines a factor in the stackup of the layers of a high-speed board.

Electromagnetic fields are always present when energy flows from one place to another, causing the return current (current must flow in a loop and return to its source). Fields are a major concern in high-speed designs because they change very quickly, which enhances their ability to interfere with everything else. Planes on adjacent layers minimize that effect.

Rise Time

A very important factor in high-speed designing is rise time. It is far more important than clock speed alone. By definition, rise time is the time needed for the signal to rise from 10% to 90% of its total amplitude as it turns on, or fall from 90% to 10% of its amplitude as it turns off. When the energy of a signal rises in a very short period of time, there are more harmonics at a higher amplitude that must be dealt with. Plus, the frequencies of the entire bandwidth from the clock through the highest harmonics of the signal must be considered. All this leads to the increased possibility of interference with everything around the signal.

Crosstalk

Crosstalk is the transfer of energy from an active source to a victim, so it is imperative for the designer to know all the sources of noise in the circuitry. As rise time shortens, the possibility of crosstalk increases dramatically. Some other factors that increase crosstalk are close traces (in x, y or z directions), wide traces, traces far from a return plane, traces crossing a split in a return plane and long traces without termination. Parts with a small signal swing are most susceptible to problems from crosstalk because they have less tolerance in their noise margin.

Crosstalk must be avoided as much as possible through careful design. Extra spacing should be used around clock signals, memory circuits, periodic repeatable signals and switching power supplies. Internal routing of most, if not all, nets is helpful. Limiting traces routed in a parallel manner either on a single layer or layer to layer will limit the buildup of crosstalk between them. Good designs will always have planes close by every signal layer for return current, and will control rise time and signal strength with termination.

Reflections

Ideally, a signal traveling down a trace from a source to a load would have all the energy transferred to the load. Unfortunately, it doesn't usually work that way. If there is too much energy to transition smoothly, a reflection forms in the opposite direction that can cause distortion to the original signal, false triggering to other ICs, and crosstalk and EMI problems to the area of the board.

Reflections are caused by inconsistent trace geometries, changes in routing like Y-splits, long stubs and fast signals on traces that are too long without termination. Reflection problems can be minimized by careful placement of parts to set up good routing schemes, limiting stubs to 1/8 rise distance, limiting the length of high-speed traces to below termination length (TABLE 1) and using termination devices.

Termination

Termination devices absorb the excess energy at the load devices. There are two major kinds of termination and they should not be combined on a single signal.

Parallel termination devices control excess energy at the last load, and should be placed at or just beyond that load. They provide a constant logic level on the line, but are a constant DC load (power drain). Some logic families require this kind of termination. Thevinin and RC terminations are forms of parallel termination.

A series terminator is placed near the source of the signal. It causes the signal on the trace to have the voltage needed. Because of the high impedance of the load, a reflection is still formed that causes the signal to double in strength, reaching the full voltage needed and thus to turn on the loads on the line. This is called reflection mode switching. The termination method should be used as often as possible within the timing budget, as it uses less power and is best for EMI purposes.

Impedance Control

The goal of impedance control is to maintain constant impedance, or at least control the impedance within tolerable limits. This is usually done by controlling trace width, controlling trace proximity to planes in the stack, and controlling trace proximity to other traces and planes on the same layer. There are many software of differing accuracy that is made to help configure those factors. It is usually best to use the same software the fabricator uses for consistency reasons. If the fabricator uses software that is not affordable, there are equations that can be used in a spreadsheet format by the designer. Any differences between the fabricators' calculations and the designers' calculations should be discussed. The fabricator's goal is a board that can be easily built, but there may be other issues that are important to the board designer that must be given equal consideration. Consistency in impedance requires cooperation and coordination between the designer and the fabricator to optimize success.

Other Factors in High-Speed Designing

The stackup of a high-speed board can be critical and should be planned very early in the design process. Early planning will help set up layer paired routing--the routing of a signal trace on the layer adjacent to either side of a plane as it changes directions: N-S, or E-W. This makes for a very clean return path, which contributes to good signal integrity. It is also important to have at least one good pair of power and ground planes very close together in the stackup for high frequency capacitance.

Placement and routing are also important issues. Parts should always be placed for best signal integrity as opposed to orientation conformity, and grouped by frequency, logic family, voltage and function. Plan the routing strategy that will be used while the parts are being placed. The designer must know where the drivers and loads are to plan for the cleanest routing scenario. Signals should be routed within their own plane return areas so the return loop is small and the signals of one voltage do not reference return planes of a different voltage. And signals should never be allowed to cross splits in reference planes.

The power distribution structure of the board is also a factor of signal integrity, because if there is not sufficient power provided in the time frame needed, switching noise can result. Capacitance in the form of caps and planes is needed to help supply power needs for the board. Bulk caps provide lots of low frequency power to the local capacitors and the planes and should be placed at the power input or the power supply. Local capacitors provide a higher frequency of power, but in smaller amounts. They are generally placed very close to the power pins of the ICs. The highest frequency power is needed for immediate activation of the high-speed parts, and comes from the inter-plane capacitance, but in very small amounts. Because of the inductance of the traces between the power pins and the planes, their connections should be as short and direct as possible.

The ideas presented here are generalities and apply to designing high-speed boards in most cases, but definitely not to all. The faster the speed of the parts and signals, the more exceptions there will be to the ideas presented here. It is extremely important to read and learn about the factors involved so as to understand when the rules need to be broken, and which ones should be given priority in different circumstances to achieve the optimal designs.

SUSY WEBB is a senior PCB designer at Fairfield Industries. She can be reached at [e-mail].

TABLE 1 Termination Length by Family

                           MAX LINE    MAX LINE
                            LENGTH      LENGTH
                           --INNER     --OUTER
DEVICE TYPE     RISETIME   (in./mm)    (in./mm)

Standard TTL    5.0 nSec   7.27/185    9.23/235
Schottky TTL    3.0 nSec   4.36/111    5.54/141
10K ECL         2.5 nSec    3.63/92    4.62/117
ASTTL           1.9 nSec    2.76/70    3.51 /89
FTTL            1.2 nSec    1.75/44     2.22/56
BICMOS          0.7 nSec    1.02/26     1.29/33
10KH ECL        0.7 nSec    1.02/26     1.29/33
100K ECL        0.5 nSec    .730/18     .923/23
GaAs            0.3 nSec    .440/11     .554/14
Other           0.1 nSec    0.15/4      0.18/5

Note: Approximation calculated assuming
a nominal Er = 4.1

* Table published by Rick Hartley in his High Speed
Design Presentations