High Level Design Systems Expands Design Planning Product Line To RTL Level; New Top-Down DP Provides Accurate Prediction of Chip Level Performance During RTL Design.

SANTA CLARA, Calif.--(BUSINESS WIRE)--Feb. 19, 1996--High Level Design Systems (HLDS) today announced the availability of Top-Down DP, the industry's first floorplanner that combines production-proven floorplanning techniques with unique HDL estimation and analysis technology to provide IC designers accurate prediction of chip-level performance characteristics, such as size, timing and power consumption for deep submicron IC designs.

Focused exclusively at the Register Transfer Level (RTL), Top-Down DP allows design cycle times to be significantly reduced by uncovering and fixing major design problems associated with the physical implementation of a design at the HDL entry phase when they are least expensive to fix.

Top-Down DP reads and analyzes HDL code to generate estimates for size, timing and power. Top-Down DP automatically creates a chip-level floorplan which allows designers direct access to deep submicron physical implementation information, such as top-level interconnect parasitics, that are crucial to accurately predict chip-level performance characteristics.

Introducing "physical reality" to the HDL design phase allows Top-Down DP to reduce the number of iterations between RTL design and synthesis step to place and route step, dramatically reducing design cycle time and significantly shortening time to market.

RTL Prediction Issues

Existing design methodologies assume that size, timing, routability and power dissipation can only be accurately predicted after the logic synthesis step. In submicron design, mismatches between the architectural design intent and physical implementation cause tools like synthesis to produce circuits that are difficult to implement, are excessively large and can have significant routability problems.

Designers are then forced to spend large amounts of time in synthesis or logic design while problems actually lie in the original RTL level design. The lack of RTL level analysis forces designers to analyze logic netlists rather than design architecture.

"Performance, power dissipation and chip size problems often must be fixed by making architecture, partitioning, or major design changes," said Bob Wiederhold, HLDS' executive vice president and chief operating officer. "Since fixing the problems can require fundamental changes to the HDL description, a designer would ideally like to catch these problems before spending a lot of time synthesizing to the logic level and implementing the design physically."

Top-Down DP Works at Verilog RTL

Using only an RTL source level design description in Verilog HDL, Top-Down DP allows deep submicron IC designers to quickly estimate the number of gates and area for each RTL process and module, create a floorplan for the design and analyze the chip's size, performance, and power dissipation.

Since Top-Down DP operates at the HDL level, crucial architecture, partitioning and design decisions can be made before synthesizing and floorplanning at the logic level. This allows better design data and constraints to be passed to synthesis and physical implementation tools.

High Speed Proprietary HDL Estimator

At the heart of Top-Down Design Planner is the HDL Estimator, which reads in pre-synthesized Verilog HDL and produces a HDL graph-based data model for use by other Top-Down DP analysis tools. Estimation is based on a high speed proprietary compiler technology that can estimate chips of 100,000 gates or more in minutes.

The HDL Source Code Annotator tool in Top-Down DP allows a designer to see the source annotated with size information and numbers of latches, registers and multiplexers in the form of Verilog comments. This tool can be used to help designers and managers keep track of design size early in a project and also help RTL designers write better, more compact code.

Top-Down DP performs size estimation in pure gates. Optionally users can generate custom, technology-specific libraries to fine tune the estimation. Size and timing estimation with custom libraries provides higher degrees of accuracy and allows feasibility analysis to be performed early in the design process.

Designers can also override estimation analysis from Verilog comments for non-synthesizable blocks, allowing Top-Down DP's analysis tools to handle both synthesis and custom implementation. This is key in complex designs like microprocessors where some of the HDL will actually be implemented through custom logic while only portions are synthesized.

Powerful RTL Timing Analysis

Chip-level timing is analyzed by processing the proprietary graph-based data model produced by Top-Down DP's HDL Estimator. Flip-flops and latches are directly inferred and full clocking structure is directly extracted from the HDL constructs. Users specify chip clock architecture and performance goals allowing the RTL Timing Estimator to analyze inter-register or latch delays.

During timing analysis, size is adjusted for load information and analysis is performed on functional components which are likely to increase in size in order to meet estimates.

"RTL size and timing estimation creates a unique set of issues. If you estimate the size of circuit for functionality you have one set of results. When you specify timing goals, size of a circuit must be adjusted to meet these goals making size and timing interdependent. The key to RTL analysis is to be able to quickly identify unfeasible timing paths and provide realistic feedbacks to the HDL designers," said George Janac, HLDS' Vice President of Engineering.

Critical paths can be "walked" and estimated, giving designers early feedback on potential architectural problems related to clocking inconsistencies or excessive delays. Timing estimation uses the Fasnet Delay Calculator, HLDS' previously announced deep submicron delay calculator to estimate wiring delays. RC parasitics can be extracted and accurate wire load models are generated once the RTL floorplan is created in Top-Down DP's Floorplanner.

Full Chip Level Timing

Directly from the HDL source, Top-Down DP creates black box timing models which can then be combined with wire and floorplan information to perform full chip timing simulation. This powerful capability allows inter-block timing consistency to be analyzed once RTL level modules are available. Data from floorplanning is also used to analyze long wire delays which are incorporated into the simulation allowing submicron delays to be included in chip level simulation.

"Black box simulation is the key to large scale IC design. It allows inter-block timing to be analyzed without having to simulate all the details of each block. While the concept is not new, it is not commonly used because the black box model generation is a manual process without links to implementation or has to be done from actual layout. By providing automation at the RTL level `black box' simulation can be carried throughout the design process," said Janac.

Forward Timing Driven Synthesis Interface

Top-Down DP interfaces directly to Synopsys' Design Compiler. By estimating timing effects of chip-level or inter-block wiring, Top-Down DP passes the timing information in boundary constraints files to Design Compiler, allowing the synthesis tool to take into account large RC wire delays.

Realistic timing budgets passed down from Top-Down DP can also help minimize gate count and improve synthesis results. This can help minimize iterations by providing synthesis with back-end physical information from the start, rather than after a few synthesis/place and route iterations.

"The time savings possible with Top-Down DP are significant," said Janac. "To predict chip size, for example, conventional synthesis tools require the designer to actually synthesize the IC design -- a process which can take up to a day. With Top-Down DP, this prediction can be accomplished early in the design phase in as little as 20 minutes.

"Moreover," Janac added, "Top-Down DP can slash even more time from the design cycle by automatically generating boundary conditions. Designers working with existing tools must determine boundary conditions by hand; each determination requires its own iteration -- and each iteration can take anywhere from several hours to several days. In addition, code optimized early in the design process generates shorter netlists, and leads to smaller chip sizes."

Integrated RTL to Physical Design Planning Flow

Top-Down DP was developed using the same floorplanning infrastructure used in Logic DP and Physical DP, allowing smooth design flow between the floorplanning stages and transparent data movement stages. Within HLDS' integrated floorplanning environment, designers can now perform floorplanning at the RTL stage of the design process using Top-Down DP, then refine and optimize the floorplan using Logic DP and Physical DP during logic and physical implementation stages, respectively.

Pricing and Availability

Top-Down DP's U.S. list price starts at $65,000 and is available in Q2 1996. Top-Down DP, as well as Logic DP and Physical DP, runs on industry-standard workstations from Hewlett-Packard and Sun Microsystems.

High Level Design Systems is publicly traded on the Vancouver Stock Exchange (VSE:HLD.U) and is a leading supplier of open-architecture and vendor-independent design planning tools for deep submicron gate array and cell-based integrated circuit design. The Company's design planning tools provide a link between RTL design, logic and physical implementation phases, ideal for companies designing smaller and denser integrated circuits on critical time-to-market schedules. -0-

NOTE TO EDITORS: The HLD Logo is a registered trademark of High Level Design Systems. Other brands or products are trademarks or registered trademarks of their respective holders and should be treated as such. Reader inquiries should be sent directly to High Level Design Systems, 3945 Freedom Circle, Fourth Floor, Santa Clara, CA 95054. The main number for phone inquiries is 408/748-3456. Fax number is 408/748-3499.

CONTACT: High Level Design Systems, Santa Clara

Bob Weiderhold, 408/748-3456

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Michelle Clarke, 415/638-3400

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