HP Introduces Innovative Tool for ATM Design Teams; Flexible Cell Traffic Generation and Analysis at Parallel Interfaces Accelerates ATM Development.

PALO ALTO, Calif.--(BUSINESS WIRE)--Nov. 21, 1995--The process of validating, debugging and testing asynchronous transfer mode (ATM(1)) switch fabrics or chip sets -- formerly difficult, expensive and imprecise -- now is easier, thanks to a new parallel cell/traffic generator and analyzer system from Hewlett-Packard Company.

This off-the-shelf solution allows hardware design engineers to verify chips and modules at parallel interfaces such as UTOPIA(2) without having to build their own generator and analyzer system. The solution makes concurrent engineering possible, because engineers can begin design verification before a system is complete. Previously, engineers had to wait until the system was complete with all its submodules before they could begin design verification using serial protocol test equipment.

In addition, the HP E4829A provides flexible cell generation, which handles routing tags, allows users to exercise cell-switching functionality, and verifies cell integrity at standard and proprietary parallel interfaces under relaxed and stressed traffic conditions.

As a result, engineers can test ATM designs easily, thoroughly and earlier in the development cycle than before, thus reducing time to market.

APPLICATIONS

The parallel cell/traffic generator and analyzer system is targeted for semiconductor and network equipment manufacturers developing integrated circuits, application specific integrated circuits and switches. It is used during chip/module verification, switchboard debug and system troubleshooting in the following applications:

o exercising ATM switch fabrics, such as verification of

cell integrity, header translation, routing-tag handling

and cell-delay variation measurements;

o verifying ATM layer functions such as traffic shaping,

cell insertion/discarding, policing functions; and

o verifying functional PHY devices, as well as first in,

first out (FIFO) stressing. PHY is the bottom layer of

the ATM protocol stack; it defines the interface between

ATM traffic and the physical media.

FEATURES

The HP E4829A parallel cell/traffic generator and analyzer system provides active stimulation and active/passive analysis of cell traffic at 8-bit UTOPIA level 1 or custom 8-bit cell interfaces. Users can set up standard and proprietary internal cell formats by combining cells with a wide choice of single segments, such as memory-based, time-stamped and standard ATM header segments. Flexible traffic-generation capabilities range from relaxed-periodic to random burst-cell traffic, allowing users to verify that their designs work under all conditions. In addition, the system provides detailed, real-time analysis of cell streams, such as cell error rate, cell-loss and cell-delay-variation measurements.

COMPLEMENTARY ATM PRODUCTS

The HP E4829A complements the HP 75000 broadband series test system. The broadband series test system addresses serial standard interfaces from cell level to protocol level, while the HP E4829A addresses internal parallel interfaces at the cell level. Although each system can be used independently, together they make a complete solution for board debugging, system troubleshooting and functional PHY device validation.

An HP E4821A parallel cell/traffic generator and analyzer module is available for the broadband series test system Form-7 and Form-13 mainframes. Although they share the same frame and workstation, the instruments are configured as independent test tools and the user interfaces run independently on two separate windows.

PRICES AND DELIVERY

For extensive chip and module validation, the HP E4829A comprises the following:

o hardware module containing a complete

transmitter/receiver port --

the system has room for expansion up to eight ports;

o software module providing the ATM-specific functions for

8-bit interfaces;

o graphical user interface;

o 13-slot frame;

o embedded series 700 controller; and

o disk module.

Two HP E4889A active pods are required to connect to the device under test.

A complete setup for the HP E4829A starts at $60,000. The HP E4821A module for the broadband series test system is $30,000. Delivery is estimated at eight weeks after receipt of the order.

Future enhancements are expected to include new pods and software modules in 1996 for the upcoming UTOPIA Level 2 16-bit standard.

Hewlett-Packard Company is a leading global manufacturer of computing, communications and measurement products and services recognized for excellence in quality and support. HP has 102,300 employees and had revenue of $31.5 billion in its 1995 fiscal year. -0- (1) ATM stands for asynchronous transfer mode. This is a high-speed, switching and multiplexing technology that uses 53-byte cells (5-byte header, 48-byte payload) to transmit different types of traffic simultaneously, including voice, video and data. It is asynchronous in that information streams can be sent independently without a common clock.

(2) UTOPIA stands for Universal Test and Operations PHY Interface for ATM. This defines the interface between the physical-layer (PHY) and upper-layer modules, such as the ATM layer. -0-

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