Going mainstream with chip-on-board: successfully merging COB with surface mount requires controlling a new set of complex variables related to the wire bonding process.

Chip-on-board (COB) and integrated circuit (IC) packaging share a common heritage with roots entrenched deeply in the wire bonding process. Thereafter, any similarities end; the great divide between them is the subsequent steps and processes. COB technology includes variants such as chip-on-flex (COF) or chip on other substrates. The fundamentals of the process involve attaching the chip (die) in place and wire bonding it directly to the substrate metallization. In essence, the packaging and testing task transfers from the IC backend process to the board assembly shop. The process eliminates any other package in between, thereby significantly improving footprint efficiency and cutting cost and lead time.

COB technology is at work in many products, but process information has remained somewhat limited possibly because wire bonding has more in common with IC backend processes than with traditional surface mount assembly. The merging of COB with mainstream surface mount processes has meant acquiring specialized knowledge, usually through hands-on experience. Surface-mount assemblers should be aware of the requirements for merging COB processes into existing surface-mount lines or managing existing COB yields.

Diverse COB Applications

Portable electronic appliances are major consumers of bare dies using COB assembly on organic substrates. Included are applications such as personal digital assistants (PDAs); pagers; watches; calculators; videocams; electronic books; dictionaries; spellcheckers and translators; personal medical devices like blood glucose testers, hearing aids and other monitoring devices; and a wide range of toys and handheld games.

Radio frequency (RF) modules use gold wire or ribbon bonding of gallium-arsenide (GaAs) devices without encapsulation on ceramic or teflon substrates. Chip-on-flex head preamplifiers (Figure 1) are found in computer disk drive head stacks. However, this application is migrating toward flip-chip on-flex and possibly chip-on suspension (COS). Other applications for chip-on-flex include folded assemblies for digicams and videocams.

[FIGURE 1 OMITTED]

One or two COB devices per assembly are common, but some applications may use as many as six COB devices on one board. COB is essentially the grassroots technology behind many plastic ball grid arrays (PBGAs), array chip-scale packages (CSPs) and single inline packages (SIPs). CSPs with multiple stacked dies are now a reality. With two-up or three-up die stacks, footprint efficiencies become well above 100 percent, exceeding, those of flip chips. Conceivably, this capability may someday extend to COB surface-mount assemblies.

COB Positioning

The cost per pin for the more traditional packages like quad flat packs (QFPs) and small outline integrated circuits (SOICs) has nearly flattened out at around 0.25 to 0.50 cent, depending on size and volume. One reason lot these stable prices is that traditional IC packaging and test equipment has already been amortized over the years. The other reason is the astronomical volume of these traditional packages.

In comparison, the prices for some newer packages like lead-frame CSPs may range between 0.40 to 1 cent per lead and 0.50 to 1 cent per sphere for a laminate version CSP, all excluding die costs. For COB, the cost per I/O charged by a board assembler comes in equal or marginally higher than the equivalent cost of packaging and testing the same die in a traditional package. However, this cost hides the real savings. For example, the large die in Figure 2 has about 184 bonds and probably would fit in a 28-mm X 28-mm QFR Bypassing that package saves nearly two-thirds of the related PCB real estate.

[FIGURE 2 OMITTED]

COB can also be used in applications where packaged devices are simply too large to fit and that require the space saving and low profile features, but not necessarily the footprint efficiency or speed performance, of a flip chip. For example, Figure 3 shows two COB devices on a 25-mm diameter board in a wrist-worn, heart rate monitor. Other examples include remote controls on personal audio equipment like minidisk and CD players. COB assembly allows the unit to blend in with the headphone wires.

[FIGURE 3 OMITTED]

A major intangible factor favoring COB is the reduction in lead time. With COB, the board assembler procures dies straight from the lab house, eliminating packaging and testing and saving weeks on IC lead time. Time-to-market can be a major success factor and, combined with real estate savings, easily offsets the modest cost increase of the COB process. This consideration is particularly true of products in fast moving markets where cost effectiveness and being ahead of competition are key to their marketability.

Die Quality and Reliability

Die quality impacts on final assembly are an important consideration for an assembler. Electrical probing at wafer level (EWS) has limitations that seldom yield confidence equal to exhaustively tested and burned-in ICs. IC level quality and reliability assurance pose challenges to implement at die level and certainly so at the consumer's price expectations. The true intent of the known good die (KGD) standard, that bare dies equal packaged IC quality and reliability, fails short of reality.

Initially, the semiconductor industry shrugged at the newer, direct-chip-attach technologies. But escalating demand for bare dies is a driving dynamo, leveraging pressure toward KGD. Interim measures include temporary die test carriers, but these risk die damage. Wafer-level burn-in to detect die infant mortality and improve reliability poses challenges in managing kilowatts of energy and other issues. Major hurdles center around costs and maintaining die integrity. Although defect levels have reduced over time, evidently more work must be done.

The Ultimate Cost Factor

Die selection for COB requires accepting and dealing with the reality of unknown bad dies (UBD) within the so-called KGD population. UBD are either defective, weak or marginal and may fail during subsequent COB processes. The Semiconductor Industries Association (SIA) 1992 roadmap envisioned a milestone at or below 100 parts per million (ppm) defects for year 2001. (1) However, the industry average is not at that level yet.

If the KGD program compliance relies purely on die yields, the dependency variables such as process technology, die size and complexity, wafer diameter and foundry maturity must all be considered. The JEDEC standard JESD49 covers requirements for information on die procurement but leaves considerable leeway for supplier discretion on data. (2) Die yield data is usually proprietary and is the very data the assembler needs.

Even as progress is being made, the board assembler must be prepared for defective dies and process yield loss. Currently, COB processes are better suited for consumer or commercial grade applications using relatively modest cost dies, ranging from under $2 to $5 per die. However, they may prove too risky and not robust enough for industrial or high reliability applications involving expensive application-specific integrated circuits (ASICs) or complex very large scale integrations (VLSIs) that are hard to test.

Die Sizing and I/O for COB

Dies used for COB on surface-mount assemblies should typically target under 200 wire bonds per die. Smaller dies are more reliable for COB due to the inherent coefficient of thermal expansion mismatch between the die (silicon at 2.3 ppm/[degrees]C) and the substrate (FR-4 at 18 to 25 ppm/[degrees]C). Similarly, small signal devices fare better than those that dissipate heat, as in power applications. Large sizes increase the probability of "popcorn" effects if the COB is subjected to reflow thermals; the assembly behaves like packaged ICs.

Die sizes are application dependent. For example, large dies could be 270 x 300 mils or 350 x 350 mils. These dies have pad sizes of 3 x 3 mils and interpad pitch of 4 mil. LCD drivers, some ASICS, microprocessor units (MPUs) and microcontroller units (MCUs) are good candidates for COB applications.

Process Considerations

The process flow for COB in surface-mount assembly is depicted in Figure 4. Several key factors must be considered for a successful surface-mount/COB merger.

[FIGURE 4 OMITTED]

Process sequence

Option 1. In a standard design, the surface-mount assembly precedes the COB process. The surface-mount process has traditional assembly steps and may be full dual-side surface mount or mixed. Option 1 protects the COB from reflow soldering thermal excursions and stress. The disadvantage is the increased possibility of board contamination, which, if excessive, could lead to bonding problems.

Option 2. In exceptions where the board design or layout is not ideal, tire COB process precedes the surface-mount assembly. The major situation is where the bonding tool interferes with other surface-mount components around the COB site due to tight spacing and insufficient clearance. One alternative is to use deep access bonding, which is expensive. The other alternative is to do COB first.

Option 2 complicates paste printing. The printing stencil needs a large opening in the COB encapsulated area. This opening must be sealed with a film-like membrane that is thin enough to adapt to the COB form and yet durable enough to withstand the rigors of thousands of print cycles. Also, the squeegee design must deal with conflicting requirements of adapting over the protrusion, yet printing uniformly everywhere else.

Overall, the printing is marginalized with poor gasketing, excessive paste bleed-through and deposit inconsistency around the COB area. Selective printing is possible if the layout permits, but this approach robs process efficiency. Alternatively, paste may be dispensed at the affected sites, but this approach is inefficient and precision dispensers are costly. Accordingly, Option 1 remains the preferred sequence, giving easier to manage tradeoffs.

Wire bonding and equipment

Of the principle types of bonding, two types--gold ball bonding and gold wedge bonding--are used in higher end and industrial applications, RF modules and manufacturing such as lead frame ICs, BGAs and many CSPs. Both types require substrate heating to 200[degrees]C or higher, depending on the type.

The third type of bonding--aluminum-silicon (AlSi) wedge bonding--is well suited and prevalent in COB applications. Aluminum wire is cheaper, and the bonding is done at room temperature, making it ideal for organic substrates while minimizing die stress. Wedge bonding tools must be ground to very narrow profiles for fine pitch capability, but their profiles can reduce loop height, an important consideration for low profile applications. Wedge bonding tools for aluminum wire are cheaper than those for gold wire; tungsten carbide versus titanium carbide, respectively. However, wedge bonding tools must maintain bond-to wire orientation so the job or tool must rotate, making it slower.

Critical factors are controlling heel cracks and footprint shape, both relating to tool shape and maintenance. Figure 5 shows a typical wedge tool with some of the significant profile considerations such as the desired vertical relief height, wire loop height, effective loop height and the effect of back radius (BR) and front radius (FR). Other significant tool considerations are the footprint (flat or concave), hole shape (round or oval) and the wire angle.

[FIGURE 5 OMITTED]

These interactive variables must be optimized to obtain the desired bond characteristics and bond strength and to control heel cracks that occur due to crystallization and hardening at the wire-footprint junction. For example, a sharp wire transition angle can lead to fractures. The obvious cracks can be detected; the latent ones cause grief, giving test intermittence and reduced thermal cycle life. Bonding tools require effective cleaning and maintenance programs, and tool life is about 400,000 to 700,000 bonds.

Bonders are judged on bond quality. The key selection criteria are bond time, force and power range programmability, type of bonding, vision system, pitch capability, speed and cost performance. Prices run from around $65,000 to $200,000 depending on bond type, pitch and throughput capability. High-end speeds are around 0.2 second per bond; and to low-end speeds are 0.3 to 0.5 second per bond. Table 1 lists some typical equipment specifications and capabilities.

Die placement and attachment

Dies come either in wafer form, requiring mounting and dicing, or as prediced wafers on tape for auto die-attach machines or for pick-and-place onto die carriers. A common mode, pre-cut dies in waffle packs are well suited for semi-auto or manual assembly.

Moisture sensitivity mandates the storage of raw dies and wafers in temperature- and humidity-controlled dry cabinets with nitrogen purge. The process environment must also be well controlled because epoxy-coated die will absorb moisture once removed and must be encapsulated within 24 hours.

Die attach materials are silver-filled, single-part epoxies. Important material selection criteria include excellent thermal and electrical conductivity, viscosity and rheology to minimize tailing and stringing during dispense. Automated dispensers may be justifiable if dictated by end-product precision and throughput requirements. Manual assembly relies mostly on skilled operators using time and pressure method dispensing, with the dispense pattern being a diagonal cross.

Die placement can be automated if justified. A typical wafer-form die pickup and attach machine averages around $120,000. In manual applications, dies are typically picked from waffle trays by a rubber tipped vacuum pen. A skilled operator assisted by a 3-diopter magnifier can achieve the placement accuracy needed in about 30 seconds per die. Any x, y and [theta] (theta) shifts are adjusted out by the bonder's vision system, referencing off alignment marks and die outline. Dispensing and die placement need visual inspection and pre-and post-die attach cure.

Most critical at this stage is pick-up tool tip maintenance and control of die tilt. Damaged and contaminated pick-up tips can quickly trash dies. Post-cured die tilt of even a few mils creates pattern recognition problems leading to misbonding.

Pad metanization, layout and component clearances

For aluminum-silicon wire bonding, the copper is plated over with 75 to 100 micron nickel and 3 to 4 micron gold flash. Nickel alone is also used in some applications.

For gold wire bonding, 10 to 20 micron gold plating is preferred. Thicker gold favors wire bonding, but gold intermetallics give brittle soldering. Selective plating is a possible, but expensive, option for select applications.

The following parameters demonstrate some layout considerations:

* minimum die pad pitch = 100 microns (4 mils)

* pad die size = 75 x 75 microns (3 x 3 mils)

* minimum PCB pad size = 5 mils x 20 mils; this pad length allows rebonding room in case of rework

* minimum PCB pad pitch = 10 mils

* maximum wire length = 200 mils

* wire diameter = 1 mil

* wire loop height = 5-15 mils

* maximum die to PCB pad wire angle = 45[degrees], to prevent wires crossing adjacent die pads.

For clearances, the Option 1 flow needs a no component zone and a height limitation zone around the COB site to allow the bonding tool to operate safely. Clearance requirements are machine- and tool-specific and determined from machine specs. The Option 2 flow needs a minimum 5 mm no-component zone around the COB post-encapsulated site.

Cleanliness and contamination control 

The COB assembly requires a Class 10,000 or better cleanroom, bunny suits, facemasks and cleanroom handling discipline and control. However, all processes must be examined for contamination potential. Reflow ovens should be meticulously clean of micro solder balls and flux residues. Any offline operations involving human contact are possible sources of organic contaminants. Ultrasonic bonding energy, is sufficient for normal oxide Films and tarnish but not for excessive amounts of contamination. Plasma etching is needed to obtain the requisite bond strength and reliability for high-end applications, disk drive COF and BGA assemblies.

The frayed edges of punched printed circuit boards (PCBs) can shed fibers on the board surface, leading to misbonds. So an effective tool sharpening and control program must be used at the raw lab house. Pre-bond blowing with dry air or nitrogen assists in micro debris and particulate removal. The discerning COB assembler opts for routed PCBs instead of punched PCBs.

Bonding parameters and process control

Bond power, time and force settings depend on bond type and application and are critical during machine setup. The ultrasonic energy must be enough to bare the active metals for intermetallic bonding and yet maintain die integrity. Excessive bonding energy can lead to die stressing, cracking and cratering, some of which may surface during reliabilily testing.

Figure 6 shows the interactive wire bonding variables; the process is obviously complex. Optimization of the variables is best done through design-of-experiments (DOE).

[FIGURE 6 OMITTED]

Bond strength is the final measure of bond quality and reliability. Aspects relating to bond strength and its measurement are defined under the MIL Standard-883 method 2011.7, which is useful for initial qualification and for ongoing statistical process control. (3)

Testing

The COB process flow needs pre-encapsulation tests, which include a total static current test to validate basic connection and die integrity followed by a functional test (FT1). After FT1, a protective encapsulation is applied over the COB and cured. A critical factor is allowing the post-encapsulated assembly to cool and stabilize prior to the second functional test (FT 2), essentially a repeat of FT1, to ensure post-encapsulation bond integrity. Careless or excessive handling of the hot assemblies immediately following cure may cause bond failures.

This three-step test regimen improves finished assembly test yields and moves fault detection to the pre-encapsulation stage where COB rework is easier. Upon process maturity, FT 2 may yield levels high enough to skip it altogether.

The test regimen works for either flow: surface-mount before or after COB. with surface-mount before COB, the test fixtures are simplified because the assembly is essentially complete. With surface-mount after COB (Option 2 flow), test fixtures need an auxiliary board with just the surface-mount components (no COB devices) connecting to the COB assembly under test via test pins.

Functional test can be as simple or as thorough as needed depending on the completion level of the assembly. In-circuit test (ICT) of the assembly is a nice option, and preferred, but feasible only if the assembly is designed for it and if the value-add justifies the ICT equipment cost.

Encapsulation materials and options

Many COB encapsulation materials are single-part semiconductor epoxies. The critical selection criteria are rheology, glass transition temperature, coefficient of thermal expansion, low ionic contribution, easy cure and post-cure protection properties. Thermoset coatings typically require 3 to 6 hours of curing at 120[degrees] to 140[degrees]C. Ultra-violet curable rivals are coming along, claiming improved protection.

A glob-top is obtained by a free flow of high viscosity coating. Glob-top is easier but suffers from footprint and consequential height variability and is suited for less critical applications. Control of encapsulation height is crucial for reliability; too close to the bond wire loop or wire exposed causes failures. Precise height and footprint require an auto dispenser using Archimedes valve or positive displacement methods and can cost up to $300,000.

Dam and fill lays down a contiguous high viscosity bead, creating a well-defined containment (Figure 7). This dam is typically pre-cured for 2 to 5 minutes. The fill is a low viscosity spiral pattern using precise dispensing guidelines. Encapsulant materials must be preconditioned and the board temperature elevated to around 80[degrees]C to minimize air bubbles and moisture entrapment to prevent "popcorn" effects.

[FIGURE 7 OMITTED]

Analyzing Failures and Improving Yield

Failure analysis poses the most challenge among all of the steps in COB assembly. All surface-mount skills are useless for die-related analysis. However, die-level visual inspection can be learned and is accomplished at 50x to 500x to detect lab defects and surface damage. MIL-Standard-883-E method 2010.10 defines the visual criteria governing bare die acceptance. (3)

Mounted and bonded dies can be removed, the aluminum wires and pads chemically etched to expose the underlying silicon and the substrate can be examined for cracks and damage causing leakage currents. Once encapsulated, analysis becomes much more difficult. Decapping with fuming nitric acid is not successful; the coating simply turns to a goopy mess. The assembler can only rely on electrical testing and analysis. Ongoing reliability testing (ORT) via thermal cycling is a good tool to weed out weaknesses and improve the process.

Die-level analysis may prove quite unsettling for a board assembler. Developing a close alliance with a capable laboratory that specializes in this task and with the die supplier greatly helps. A COB problem could be a legitimate die problem or board assembly related. The assistance of wafer fab engineers, lot yield data and detailed die structure are often needed for resolution. Without that cooperation, accurate determination may not be possible.

COB Reworkability

Quality purists will probably raise their eyebrows at the thought, but rework is a necessary evil. Some dies will inevitably fail, and die selection may not always be optimal. However, not every defective COB assembly has to be scrapped. The rework process can be applied under three different scenarios:

* missing bonds or mis-bonds

* die removal and replacement before encapsulation

* die removal and replacement after coating.

Missing bonds or mis-bonds

Rework is possible only if the space around the die pad and board metallization permit bonding a new wire without disturbing adjacent bonds. The bonds must be on fresh areas and never over previous footprints. If space limits access, the die must be completely removed and the processes redone, per the following section.

Die removal/replacement before epoxy coating

This case occurs when a die is found defective at visual manual inspection or during the testing before encapsulation. The first step is to remove the bond wires with a sharp needle under magnification.

Next, controlled localized heating (typically around 200[degrees]C) is used to soften and break down the die bond adhesive. Heating is mostly top-side convective but could be radiant. Critical factors are controlling maximum temperatures and keeping gradients under 3[degrees]C/second to prevent degradation of any sensitive components. The defective die is easily pried off after the adhesive breaks down.

After a visual inspection for any site damage, remnants of the die-attach and bond wires are removed, and the site is cleaned thoroughly and re-inspected. The process then follows the prime sequence except new bonds must be on new areas and never over previous footprints.

Die removal/replacement after coating

When a fully completed and encapsulated assembly tails final test and the fault is traced to the COB, the defect could be either the die or bonding. Rework requires removing the encapsulation followed by the sequence above. As with die removal, the encapsulation is softened to the point of degradation by topside convective heating. When it loses its bond to the base material, it is then pried off. The steps then proceed as described previously.

COB rework is not pretty, but it is possible and may help recover as much as 80 percent of defective assemblies. The process nature and pad width limit rework to one time.

Conclusion

COB is a viable process for many applications. The key requirements are relatively modest cost products with relatively short life cycles and last time-to market. Die cost, sizing, I/O, complexity, foundry maturity and UBD are key factors in selecting dies for COB.

Successfully merging COB with surface-mount assembly requires understanding and controlling a new set of complex variables related to the wire bonding process. A 10,000 or better cleanroom and associated discipline are highly recommended. Challenges for the board assembler lie in acquiring the skills, knowledge and resources more attuned to IC backend processes and coupling them with surface-mount assembly knowledge.

The critical factors include a COB-friendly PCB layout, die supplier management, bond reliability and a pre-encapsulation test regimen. Critical process control points are contamination control, tool management and wire loop and encapsulation height control. Higher end applications and component manufacturing like BGA assembly require plasma cleaning. Although flip chips and flip chip CSPs compete with COB, each is unique and has its own "best-fit" market segments. GOB is a mature process, using state-of-the-art equipment. It is currently applicable to a wide range of products as a DCA alternative to IC packaging.

TABLE 1: General specifications for some common COB bonders. *

Specifications                    Bonder 1       Bonder 2

Type of bonding                   AI wedge       AI wedge
Bond force (gm)                    15-60          15-200
Bond time (millisec)               0-255       Programmable
                                Programmable
Bond power (W)                      0-1            0-1
Z travel limit (mm)                  6              10
Z travel resolution (microns)       1.6             10
[theta] limit (degrees)          [+ or -]
                                    180
[theta] resolution (degrees)       0.0125
Wire size (mils)                   0.8-2           1-2
Cycle time (millisec)               280            350
Bonding area (in.)                8x4/14x4         4x8
X-Y resolution (microns)             1              5

Specifications                    Bonder 3       Bonder 4

Type of bonding                     AI &           AI &
                                  Au wedge       Au wedge
Bond force (gm)                    15-200
Bond time (millisec)            Programmable
Bond power (W)                      0-1
Ztravel limit (mm)                   10            14.4
Z travel resolution (microns)        10            0.29
[theta] limit (degrees)
[theta] resolution (degrees)                       0.04
Wire size (mils)                     2           1-3 (AI)
                                                0.7-3 (Au)
Cycle time (millisec)               250            <166
Bonding area (in.)                  3.3           2.5x2.5
X-Y resolution (microns)             5             0.1

Specifications                    Bonder 5

Type of bonding                     AI &
                                  An wedge
Bond force (gm)
Bond time (millisec)
Bond power (W)
Ztravel limit (mm)                  12.7
Z travel resolution (microns)       0.29
[theta] limit (degrees)
[theta] resolution (degrees)        0.04
Wire size (mils)                  1-2 (AI)
                                 0.7-2 (Au)
Cycle time (millisec)               200
Bonding area (in.)                 16x14
X-Y resolution (microns)            0.1

(* based on manufacturer's published data)

Acknowledgments

Many thanks to Banlue Kitkamjornkul, process engineering manager, Wirat Sriamonkitkul, director of engineering, and Ken Hendrickson, senior director of engineering and quality, all with ACT Thailand.

References

(1.) SIA 1992. SIA Roadmap. San Jose, CA: Semiconductor Industry Association.

(2.) JEDEC. 1996. Standard JESD49 Procurement Standard for Known Good Die. Arlington, VA: JEDEC Solid State Technology Association.

(3.) MIL-STD-883-E, Test Methods Standard Micro circuits. Greensburg, PA: MIL-Standards.com,

Mukul Luthra is the business director with Waterfall Technologies, Georgetown, Ontario, Canada; e-mail [e-mail].