Galileo Technology introduces PCI system controller for R4600/R4650/R4700 CPUs; single chip solution reduces design time and complexity.

SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 12, 1995--Galileo Technology, Inc. today introduced the GT-64010, a high performance single-chip system controller that supports the IDT R4600, R4650, and R4700 64-bit RISC CPUs.

The GT-64010 is a highly integrated implementation that offers the blocks most commonly required in high performance embedded systems that use RISC microprocessors. It incorporates a 64-bit CPU interface, a DMA controller, a DRAM and Devices controller, and a PCI interface. Its highly orthogonal architecture and internal de-coupling of buses, result in a high-performance implementation that allows multiple operations to be performed concurrently, significantly reducing system bottlenecks.

The GT-64010 is the first chip in the market that addresses the convergence of affordable 64-bit RISC processors with the growing use of the PCI bus in the mid-range and high-end of the embedded market. The only options available so far to embedded users of the R4XXX CPUs have been to design their own ASICs via a costly and time-consuming effort, or to design their own FPGAs, resulting in a very costly implementation. The GT-64010 offers a superior alternative when compared with these options.

"The R4600/R4650/R4700 constitute one of the most successful RISC processor families in the high-performance embedded market in terms of new design wins. We attribute this success to the fast growing need for higher performance systems in areas like data communications, telecommunications, digital video distribution, and color printers," said Manuel Alba, President of Galileo Technology. "The GT-64010 offers 4 distinct advantages to designers of these systems: it simplifies the design effort significantly by virtue of its high integration and programmability, it extracts the maximum performance possible from the CPU due to its high-end architecture, it offers state-of-the-art connectivity and expandability through its PCI interface, and it increases the cost-effectiveness of the end equipment because of its outstanding value."

The GT-64010 is also highly flexible in the type and cost of external memories it supports, allowing users to implement low cost minimal parts-count systems or maximum performance systems with more external parts.

Technical Attributes

The CPU interface is 64-bits wide, and operates at up to 50MHz, supporting an 80MHz or 100MHz CPU in divide-by-2 mode, a 133MHz or 150MHz CPU in divide-by-three mode, and higher frequency CPUs in divide-by-4 mode. It also incorporates a 64-bit wide, 8-level deep Write Buffer that can absorb up to four CPU transactions to sustain a high level of performance. The CPU interface supports the bi-endian options of the CPU, and is directly compatible with Galileo's own GT-64012 Secondary Cache Controller.

The DRAM controller supports both standard page mode and EDO DRAMs, with an address space of 512MBytes. It supports 1 to 4 banks directly, in 32-bit or 64-bit wide configurations. For cost-effectiveness, the DRAM interface from the GT-64010 is 32-bits wide, but dedicated signal pins are incorporated to control external latches and transceivers to provide an optional 64-bit read data path directly to the CPU. This way, a 64-bit write data path for DRAM and Devices is provided through the on-board Write Buffer, and a 64-bit read data path is provided through the controlled transceivers. Accesses of 7-2-2-2 to DRAM are supported, as well as optional external parity.

The Device controller offers 5 Chip Selects, all of which feature programmable timing, thus supporting several device types, including Flash, EPROM, SRAM, FIFO, Boot Devices and I/O Controllers. The address space supported is 160MBytes, with programmable wait states. Devices supported can be 8-bit, 16-bit, 32-bit, and 64-bit wide, thus providing flexibility to the designer to select the optimal cost/performance. For instance, in some applications code could run directly from 64-bit wide Flash, and in some others a simple 8-bit wide ROM could be used and data could be loaded into DRAM at boot time.

A key feature of the GT-64010 is its DMA controller, which includes four independent DMA channels with a host of performance-oriented features. These channels can operate in chained mode via linked lists of records, a key feature for communications applications, where several packets that constitute a message need to be interlinked. The DMA controller also supports byte alignment on source and destination, and transfers data through an internal 32-byte FIFO for high performance. The DMA controller allows for very efficient data transfers between the PCI bus, DRAM, and Devices.

The PCI block of the GT-64010 is one of its most distinctive features, since it is a very high-performance implementation of what should be a high-performance bus. In contrast, several PCI chips in the market only take advantage of a fraction of the theoretical 133MBytes/sec bandwidth of the PCI bus, either due to poor architecture or to the very economical use of gates to only implement the very minimum logic that would allow a device to be called PCI-compliant. The GT-64010 actually takes advantage of most of the theoretical bandwidth by virtue of its elegant and efficient architecture, and the generous number of gates dedicated to this block.

The GT-64010's PCI block is compliant with draft 2.1 of the PCI standard, and includes posted write and read prefetch buffers of 96-bytes. It can operate as a 32-bit master or slave at up to 33MHz, supporting burst operations for efficient data transfers. It can operate as the main PCI controller on the motherboard, or as a peripheral PCI controller in an expansion card. The GT-64010 can operate as a Host to PCI bridge, translating CPU cycles into PCI I/O or Memory cycles, and generating configuration Interrupt Acknowledge and Special cycles on the PCI.

It can also operate as a PCI to Main Memory bridge, supporting fast back-to-back memory transactions, lock operations, and providing very flexible address mapping of both DRAM and Devices from the PCI side. Interestingly, this feature makes the GT-64010 a good solution for any application requiring the control and addressing of Memory from a PCI bus, even if a CPU is not present. In this particular application, the GT-64010's CPU bus is not used.

For maximum flexibility, distributed programmable address mapping is available from the CPU and the PCI bus, and all PCI configuration registers are available from both the CPU and PCI sides.

Price, Support and Availability

The GT-64010 is packaged in a 256-pin PQFP (28 x 28mm), and samples can be ordered for October delivery. Pricing for the GT-64010 is $49.95 for 10,000 pieces. The Galileo-4 evaluation board is a PCI card that will simplify the evaluation of the GT-64010. Its reference design is currently available as a technical support tool, and the board itself will be available for sale in November.

About Galileo Technology

Galileo Technology is a 30 months old fab-less semiconductor company that designs and sells core-logic chips and application-specific memories. Galileo Technology's highly integrated core-logic chips, which complement some of the leading embedded RISC microprocessors in the market, have some of the main building blocks required by performance-intensive embedded applications, like networking equipment, color printers, etc.

Galileo Technology's application-specific buffer memories use proprietary architectures that increase system performance by enhancing the interface of embedded controllers to their peripheral subsystems. Galileo Technology has 30 employees, with technical headquarters located in Karmiel, Israel, and business headquarters located in San Jose, California.

CONTACT: Galileo Technology, Inc.

Manuel Alba, 408/451-1401