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Future Design Automation Introduces SystemCenter, Expedites C to RTL Flow.


Business Editors/High-Tech Writers

Design Automation Conference 2003

SAN JOSE, Calif.--(BUSINESS WIRE)--May 19, 2003

Future Design Automation

SystemCenter's Rapd-C technology reduces code volume by 80%,

cuts development time by over 50%, targets imaging and

embedded applications

Future Design Automation, a developer of behavioral and architectural synthesis software for the EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  market, announced today that it is introducing it's first product for North America, SystemCenter(TM), a suite of co-development software tools for high-level software and hardware design and verification.

SystemCenter software increases the productivity of DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive  designers, algorithm developers, system architects, hardware designers and verification engineers developing systems on chip (SoC) that include complex algorithms. With SystemCenter, users report a 2x increase in design productivity and increased algorithm performance of up to 10x without stressing manufacturing processes.

"Since embedded system design is algorithm intensive, algorithm implementation requires co-development tools, like SystemCenter, that support ANSI-C and can be used by system architects, as well as hardware and software engineers," said Bob Barker, Future Design Automation's VP Marketing.

With SystemCenter, system architects take the functionality created by software designers, create hardware architectures and transfer the design to hardware designers for implementation in standard HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards.  environments. All these engineering disciplines can use the original C source code as a reference specification.

Proven Technology, Increased Productivity

"Future Design Automation helped increase our design team's productivity," said Mr. Haronobu Kadota, general manager, Hardware Development, OKI Information Systems. "We added Future Design Automation's system-level software to our existing design flow and reduced our code volume by 80% and our development time and manpower needs from 30 man months to 8 man months."

"Compute intensive DSP algorithms that take weeks to develop and debug in HDL code, take only days when using C and SystemCenter," added Barker.

"Over 25 leading electronics companies have used SystemCenter successfully to design embedded systems for video streaming, digital imaging, wired, wireless and encryption applications, added Future Design Automation's President and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. , Tsutomu Someya. "Their applications require fast time to market and their flows include prototyping of ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor.  designs with FPGAs."

About SystemCenter -- New Technology Moves Verification Up to the Electronic System Level

The Electronic System (ES) level of electronic design offers high level, concurrent design of hardware and software. Future Design Automation is a key player in this market.

SystemCenter software includes DesignPrototyper(TM), an architectural synthesis engine, libraries and RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences;  writers. System Center supports SystemC, ANSI-C and translates C or C++ design descriptions to RTL.

DesignPrototyper compiles ANSI-C system specifications and algorithms into hardware models. The tool utilizes Future Design's Rapid-C technology. Rapid-C technology provides interactive architectural synthesis using ANSI-C source files in a loop-and-then-branch methodology. This allows the user to perform many of the architectural verification steps while in the C environment rather than the RTL environment. SystemCenter methodology makes architectural synthesis a process of looping through, in real-time, all stages of architectural refinement, and finally branching to a hardware description in synthesizable Verilog or VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction.  RTL. Using SystemCenter, I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output.

I/O - Input/Output
 and cycle accurate system-level models can be developed. Critical architectural information is transferred when these models are output to synthesizable HDL for implementation as semiconductor devices or to hardware emulators. In addition, resources can be allocated to technology specific libraries for more specific timing analysis.

Price and Availability

SystemCenter is shipping now for Sun Solaris and Windows platforms. The price starts at $80,000 (USD USD

In currencies, this is the abbreviation for the U.S. Dollar.

Notes:
The currency market, also known as the Foreign Exchange market, is the largest financial market in the world, with a daily average volume of over US $1 trillion.
) for a perpetual license. One-year term licenses are also available. Licenses are available for ASIC and FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market.  methodologies.

Future Design Automation at DAC See D/A converter and discretionary access control.

DAC - Digital to Analog Converter
 

Future Design Automation is exhibiting at DAC in booth # 2272. To make an appointment, please contact Rich Edelman at rich@future-da.com or call 408/279-3135.

About Future Design Automation

Future Design Automation Corporation, a system-level EDA tool supplier, is headquartered in Tokyo, Japan with a North American office in San Jose, Calif. The Company's high-level design tools support C and C++. For more information, please visit www.future-da.com.

Future Design Automation is located at 675 N. First Street, Suite PH3, San Jose, CA 95112, 408 279-3135

Notes to editors:

SystemCenter data sheet and white paper are available on request.

Acronyms and definitions:

ANSI-C

C/C C/C Center to Center
C/C Combustion Chamber
C/C Command/Control
C/C Crew Chief
C/C cabin cruiser (US DoD)
C/C chief complaint (medical)
C/C Channel-to-Channel
C/C Communication and Collaboration
++

DSP

DVCon

ESL (1) An earlier family of client/server development tools for Windows and OS/2 from Ardent Software (formerly VMARK). It was originally developed by Easel Corporation, which was acquired by VMARK.  

EDA

RTL

Verilog

VHDL

DesignPrototyper and SystemCenter are trademarks of Future Design Automation Corporation.

All trademarks and tradenames are the property of their respective holders.
COPYRIGHT 2003 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2003, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Geographic Code:9JAPA
Date:May 19, 2003
Words:717
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