Fujitsu HaL develop next generation 64-bit RISC processor; SPARC 64 is first implementation of SPARC V9 architecture.CAMPBELL, Calif.--(BUSINESS WIRE)--Feb. 15, 1995--Fujitsu Ltd. and its Campbell, California-based affiliate HaL Computer Systems HAL Computer Systems was a Campbell, CA-based computer manufacturer. It was started in 1990 by Andrew Heller, a principal designer of the original IBM POWER architecture. His idea was to build computers based on a RISC architecture for the commercial market. Inc. have developed a RISC processor that is the industry's first implementation of the SPARC (Scalable Performance ARChitecture) A family of RISC CPUs from Sun that runs mostly under Sun's Solaris, but also under Linux and BSD operating systems. After development began in the mid-1980s by David Patterson of the University of California at Berkeley and Bill V9 64-bit instruction set architecture. The development is being announced today at the IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. International Solid-State Circuit Conference (ISSCC ISSCC International Solid State Circuits Conference ISSCC International Student Services Center Corporation Limited ) in San Francisco. Called SPARC 64, the processor is a multi-chip module (MCM) containing seven chips -- a CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. , four cache memory chips (64kbytes each), a memory management unit (MMU), and a clock chip -- which are mounted on a 6.13cm x 4.46cm ceramic board. The chips are fabricated using Fujitsu's twin-well, 3.3V, 0.4-micron CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. process with four layers of metalization. There are approximately 22 million transistors in total, and the effective channel length of transistors is 0.35 micron. SPARC 64 tracks 64 outstanding instructions, and utilizes register renaming and dataflow execution to achieve an estimated integer performance exceeding 256 SPECint92 and floating point performance greater than 330 SPECfp92 at 154MHz. Moreover, unlike existing microprocessors, all memory, beginning with the cache memory, features built-in error correction and detection functionality, thereby offering reliability on par with existing large-scale computer systems. "We're extremely proud and excited about our engineering effort for SPARC 64," commented Arthur G. Goldberg, HaL's executive vice president. "We believe this establishes the basis for the highly competitive products that we will be introducing." -0- Note: SPARC V9 is a trademark of SPARC International and refers to the 64-bit architecture developed by Fujitsu, Sun Microsystems and others. CONTACT: HaL Computer Systems Inc. Clark Hoyle, 408/379-7000, ext. 1391 |
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