Frontier Design Releases EDA Tools for the Creation of Re-usable DSP IP Cores.

TORONTO--(BUSINESS WIRE)--Sept. 14, 1998--Frontier Design today announced the availability of the two members of its "Algorithm-to-Register Transfer(TM) (A|RT(TM)) family of EDA tools.

A|RT Library and A|RT Builder automate the process of converting floating point DSP algorithms to bit-accurate fixed-point VHDL or Verilog descriptions. The tools are designed to help companies convert legacy intellectual property that exists in the form of floating-point algorithms to re-usable silicon intellectual property cores.

According to Herman Beke, Frontier's CEO, "The vast majority of intellectual property is literally `imprisoned' in the form of floating-point C-algorithms that have been developed over the years. A great amount of engineering expertise and hard work will be wasted, if these algorithms are not recast as re-usable silicon IP.

"However, converting floating-point algorithms to HDL cores is non-trivial because it is very difficult to maintain system behavior when these algorithms are recast in a fixed-point representation. Until now, there have been no EDA tools that support this conversion. Our aim with the A|RT family of tools is to liberate this legacy IP and make it accessible and re-usable."

The basis of any digital signal processing or communication system is a group of algorithms that perform filtering, modulation, demodulation, compression, coding and other operations on digital signals. Usually these algorithms are developed in a pure mathematical environment, using "perfect" signals and "ideal" operators.

As such, typically those algorithms originate in a floating point representation, in which word-lengths can be of any size and the number of bits of precision is assumed to be infinite. Most hardware implementation, on the other hand, is done using fixed-point arithmetic because of significant cost-saving and increased performance.

Therefore, in order to create re-usable Verilog or VHDL IP cores of these DSP algorithms, they first have to be re-designed for fixed-point arithmetic. The challenge is to make the algorithms work with fixed and limited dynamics and precision (ergo the name "fixed-point").

Fixed-point number representations can lead to a variety of problems. For example, if the fixed word-length is 16-bits with 4-bits of precision, and the result of a multiplication is 31 bits long with 7 bits of precision, the result will not fit in the specified word length. At best, this situation will cause the system to function improperly. At worst, it will result in a catastrophic failure.

The floating point result must be rounded, truncated or scaled in order to get to fit in the fixed-length word. This is much easier said than done because the C-language doesn't provide support for fixed-point data types. As a result, designers must write and simulate ad-hoc code by trial and error to get a fixed point approximation of a fixed-point algorithm. This process is time-consuming and error prone.

A|RT Library -- Frontier Design's A|RT Library allows designers to quickly develop robust descriptions of fixed-point algorithms by providing a set of C++ data classes and operators that encapsulate the characteristics of fixed-point arithmetic and that accurately accounts for quantization and overflow effects. For example, the floating-point result can be specified in fixed-point form with a 14-bit word length and 10-bit precision, by respecifying it as "Fix<14,10>". Fixed-point values can be specified as signed or unsigned fixed-point (i.e. Fix<w.d> or Ufix<w,d), as signed or unsigned integers (Int<w>, Uint<w>) or a boolean (Bool).

Bit-accurate Modeling of Quantization and Overflow -- Simply specifying fixed-word length variable is insufficient, however. The effects that result from using a fixed word-length must also be modeled correctly. These include both over flow and quantization. -0-

     Overflow -- Overflow occurs whenever a value needs to be stored
     that exceeds the maximum or minimum value that can be represented
     with a given fixed-point data type. E.g. 100 cannot be stored in
     a Fix<8,2>, as it can only hold values between -32 and +31. In
     this example 100 will actually become -27. An overflow will occur
     (typically wrap-around) with drastically changed behavior as a
     consequence.

     Quantization -- Quantization occurs whenever a value needs to be
     stored with less precision than is required to represent the
     actual value. E.g. the value 3.3 cannot be correctly represented
     with a Fix<8,2>; 3.25 is the closest approximation with the
     specified precision. The "error" that is made is typically
     experienced as "digital noise."

-0-

A|RT Library allows the designer to specify how quantization and overflow are to be handled. In situations where the fixed-word precision is less than the precision of the value to be stored, the designer may specify that the result will be truncated, truncated-0, rounded-infinity, rounded-plus-infinity, rounded-minus-infinity, convergent rounding, and rounding-zero, by simply incorporating an A|RT Library function into the operation.

Using A|RT Library, the designer can easily specify the intended quantization and overflow behavior. The following code fragment enforces wrapping overflow and rounded quantization:

fxpOqc myChar(WRAPPED,ROUNDED0);

Fix<8,7> c= oqc(a+b, &mychar);.

Including the statement "#include <fxp.h>" at the beginning of the C-description is all that is required to overload A|RT Library's fixed point data types and operators on the C code. A|RT Library allows designers to handle quantization and overflow effects in fixed-point algorithms, while maintaining the desired behavior.

Analysis and Statistics -- A|RT Library also offers built-in formatting functions and statistics classes for the purposes of debugging and analysis. As such, specifics for each fixed-point data type can be logged and analyzed. Example analysis functions are supplied for overflow logging, min-max computation, histogram and reading uninitialized memory. Many others can easily be added.

Facilitates Development for Fixed-point DSP Processors and Hardware -- A|RT Library can help designers in three ways: -0-

     1) Design and Evaluate Fixed Point Algorithms -- Fixed-point
     behavior can be simulated very quickly in C and the algorithm can
     be refined until the desired output is achieved.

     2) Model the behavior of algorithms in off-the-shelf, fixed-point
     DSP processors -- Designers can accurately model the behavior of
     C-code in several different DSP processors to determine which
     will provide the optimal implementation.

     3) Define A Hardware Implementation of an Algorithm -- A|RT
     Library can be used to define and analyze a variety of hardware
     implementations of the algorithm prior to converting it to an
     HDL. HDL simulations can take days, whereas C-simulations take
     only a few minutes. Thus, A|RT Library gives designers the
     freedom to simulate multiple hardware implementations in a short
     period of time, prior to going to an HDL. Once the designer is
     satisfied, the algorithm can be automatically converted to a
     bit-accurate representation in Verilog or VHDL, in a matter of
     seconds, using A|RT Builder.

-0-

A|RT Builder Automatically Converts Fixed-point Algorithms to VHDL or Verilog -- In just a few seconds, A|RT Builder converts fixed-point enhanced ANSI C code (A|RT Library) to a bit-accurate, synthesizable Verilog HDL or VHDL description. The HDL description can be used as the basis of a reusable IP core. The designer simply specifies the appropriate C file and selects a variety of options from a pull-down menu.

A|RT Builder can generate HDL descriptions that are optimized for HDL synthesis using Synopsys' Design Compiler(TM) and Exemplar's Leonardo and Galileo. Designers simply select their main function, entity and work files, which HDL they want generated (VHDL or Verilog), the synthesis tool they will use and the architecture in which they intend to implement the design. Designers may also specify state initialization, synchronous or asynchronous reset, flattened or hierarchical design, etc. Within a few seconds A|RT Builder creates a datapath with the exact word-sizes and resources required to accurately implement the fixed-point specification.

Test benches automatically generated by A|RT Builder can be used to compare the C-simulation to the HDL simulation to verify accuracy.

The HDL code structure generated by A|RT Builder is easy to understand with a clearly separated combinatorial and sequential processes.

Platforms and Third-party Tool Support -- A|RT Library is available for Windows 95, Windows 98 and Windows NT (using Microsoft Visual C++ or Borland C++ compilers) for PC platforms; and for Unix-based Hewlett-Packard HP-UX 10.20 and Sun Solaris(TM) 2.5 systems (using the platform and the GNU and C++ compilers).

A|RT Builder runs on Hewlett Packard and Sun workstations. Its HDL output can be used with any behavioral synthesis tool, but it is particularly optimized for use with behavioral synthesis tools from Synopsys.

A|RT Builder Output Can Be Used In Virtually Any Implementation -- The HDL output from A|RT Builder can be synthesized into any FPGA, CPLD or ASIC architecture using third-party synthesis tools. Prototypes and early product models can be implemented in programmable devices and then re-synthesized in an ASIC once the design is stable. This eliminates any re-design or re-simulation associated with ASIC conversions of CPLD designs.

Pricing and Availability -- Both A|RT Library and A|RT Builder are available immediately. A single-user license of A|RT Library costs $1,000 and can be downloaded from Frontier Design's WWW site (http:\\www.frontierd.com) or any of several FTP sites, or it can be purchased from a Frontier Design distributor. Special prices are available for 5, 10 and 25-packs. A|RT Library is included, for no additional charge, with each purchase of A|RT Builder.

Prior to January 1999, A|RT Builder is offered at a special introductory price of only $12,000. It is available from Frontier Design distributors.

Frontier Design will be demonstrating the A|RT EDA tools, as well as the company's Algorithm-to-Silicon(TM) design methodology in Booth 825, at DSP World in Toronto, Ontario, Canada, Sept. 14-16.

Frontier Design was founded in 1997 as the result of a management buy-out of the European Development Center of Mentor Graphics (NASDAQ:MENT). The firm's primary emphasis is its "algorithm-to-silicon" design methodology that greatly improves the creation of Silicon IP blocks starting from customer-proprietary or industry-standard algorithms in the fields of wireless telecom, consumer audio or multimedia applications.

Algorithm-to-Silicon IP blocks consume less power, are less costly and require substantially less development time than other alternatives. Frontier Design sells its design services and a line of EDA tools directly from its facility in Leuven, Belgium, and from its sales office in California. Frontier Design also sells through a growing number of distributors and Value Added Resellers in Northern America, Europe, Japan and the Pacific Rim.

Frontier Design's World Wide Web site is frontierd.com. Email inquiries may be sent to [e-mail].

Windows is a registered trademark of Microsoft Corporation. A|RT, Algorithm-to-Silicon and Algorithm-to-Register Transfer are trademarks of Frontier Design.

Note to Editors: The 10th, 12th, 13th, 16th and 17th paragraphs of this press release contain the "less-than" and "greater-than" symbols (e.g. "Fix<8,2>" wherein the "less-than" symbol appears before the number 8 and the "greater-than" symbol appears after the number 2). The 17th paragraph also contains the "pound" symbol (i.e. "#include" wherein the symbol appears before the word "include"). These characters do not transmit properly in some systems.

CONTACT: Frontier Design

Herman Beke, [phone]

[e-mail]

or

The William Baldwin Group

Nancy B. Green, 650/856-6192

[e-mail]