Frontier Design Introduces C-to-HDL EDA Tool for Windows NT.

LEUVEN, Belgium--(BUSINESS WIRE)--March 1, 1999--Frontier Design today introduced the world's first Windows NT-based EDA tool to support C-based language-driven system-on-a-chip design. A|RT Builder 1.5 allows designers to create efficient HDL designs from C-language algorithms by automatically converting these algorithms to Verilog or VHDL. Using a 300 MHz Intel Pentium workstation, HDL conversion requires only a few seconds. A|RT Builder 1.5 is also available for UNIX workstations.

According to Herman Beke, Frontier's CEO, "A|RT Builder 1.5 makes it possible for designers to cope with the system-on-a-chip design problem. System designers typically work in the C-language to develop and simulate their designs. Once the design works, it must be completely re-written it in HDL, a time-consuming, cumbersome process. Although designers can write the fixed-point design directly in HDL, very few system designers have the expertise to do so. Furthermore, HDL simulators are at least one order-of-magnitude slower than native C execution and they do not have the system-level application libraries, such as CDMA, GSM, RF or radar, that are required to get a reliable design. Basically, designers are stuck with the need to do the design once in C and then re-do it in the HDL.

"A|RT Builder 1.5 makes this HDL conversion effortless. It will automatically and reliably convert a fixed-point algorithm to either Verilog or VHDL in a couple of seconds, greatly speeding up the design cycle. Even non-HDL experts can use A|RT Builder 1.5 to create HDL descriptions from their C-code.

"More importantly," Beke explained, "By fostering a language-driven design methodology, A|RT Builder 1.5 gives designers complete implementation flexibility. The input C-description can be cross-compiled for execution in a processor for prototyping, and subsequently be synthesized for FPGA or ASIC implementation. This tool also gives designers the ability to optimize power consumption, performance or die size at the C-language level where the highest improvement can be achieved. Since A|RT Builder 1.5 generates the HDL quickly and automatically, designers can synthesize their designs, analyze them to determine where trade-offs can be made and then go back to the original C-language design to make those trade-offs. Hand-writing the HDL description is much too time consuming and cumbersome to engage in multiple design iterations, although a must for optimizing the design! By keeping the design at the C-level, designs are completely re-usable and re-targetable to any processor, FPGA or ASIC implementation without substantial re-design," Beke concluded.

Correct-by-construction Conversion Fixed-point Algorithms to VHDL or Verilog - A|RT Builder 1.5 quickly converts fixed-point enhanced ANSI C code (from A|RT Library) to a bit-accurate, synthesizable Verilog HDL or VHDL description. The designer simply specifies the appropriate C file and selects a variety of options from a pull-down menu. The HDL output uses the what-you-write-is-what-you-get (wywiwyg) principle so that the HDL exactly corresponds to the C-language description. A|RT Builder 1.5 has configurable C and HDL syntax highlighting to further enhance the productivity of the designer. Syntax colors and styles are user-configurable.

Optimized For Third-party Synthesis - A|RT Builder 1.5 HDL output is optimized for synthesis using Synopsys' Design Compiler(TM) and Exemplar's Leonardo Spectrum. Designers simply select, their main function, entity and work files, whether they want Verilog of VHDL output, and the architecture in which they intend to implement the design. Designers may also specify state initialization, synchronous or asynchronous reset, flattened or hierarchical design. Within a few seconds, A|RT Builder creates a datapath with the exact word-sizes and resources required to accurately implement the fixed-point specification.

Built-in functions in A|RT Builder can be used to express bit manipulations on fixed-point types that will be translated into HDL constructs that are commonly used for this purpose. These functions interpret input and output arguments as bit strings (VSI bit vector), adhering as closely as possible to VSIA standards. Bit manipulation functions include: append and concatenation; bit select; range select; and set range to value.

A|RT Builder 1.5 also allows designers to prevent the generation of latches that may be inferred by the HDL synthesis engine when a non-static variable that gets a value assigned in specific (but not all) branches of an if or switch statement. The inference of these latches is generally due to a difference in semantics between C variables (implicitly initialized to dontcare) and HDL variables (retaining their previous value). By allowing such variables to be initialized to dontcare, A|RT Builder prevents this situation. A|RT Builder automatically generates test benches that can be used to compare the C-simulation to the HDL simulation to verify accuracy.

A|RT Library - A|RT Library is a companion tool to A|RT Builder 1.5 that also runs under the Windows 95, 98 and NT operating systems. A|RT Library provides a set of C++ data classes and operators that encapsulate the characteristics of fixed-point arithmetic and that accurately account for quantization and overflow effects. The fixed-point semantics provided by A|RT Library have been proposed as the VSIA (Virtual Socket Interface Alliance) fixed-point standard and will fully support the standard once it is frozen.

Analysis tools provided with A|RT Library allow the designer to identify C-language design modifications to improve silicon efficiency, performance or power drain. For example, A|RT Library generates a histogram with the minimum and maximum values and the number of bits required to store intermediate results without distortion (ranging from 1-bit to 32-bits). This information can be used to achieve the smallest possible word-width without compromising system behavior, thereby increasing silicon efficiency.

Platforms and Third-party Tool Support - A|RT Library is available for HP-UX, Solaris, Windows(R) 95, Windows 98 and Windows NT (using Microsoft(R) Visual C++ or Borland C++ compilers) for PC platforms. A|RT Builder 1.5 runs on HP-UX, SUN Solaris and Microsoft(R) Windows NT 4.0 workstations.

A|RT Builder 1.5 Output Can Be Used In Virtually Any Implementation - The HDL output from A|RT Builder can be synthesized into any FPGA, CPLD or ASIC architecture, using third-party synthesis tools. Prototypes and early product models can be implemented in processors or programmable devices and then re-synthesized in an ASIC once the design is stable. This eliminates any re-design or re-simulation associated with ASIC conversions of CPLD designs.

Pricing and Availability - A|RT Builder 1.5 is available immediately, and sells for $20,000. A|RT Library is included, for no additional charge, with each purchase of A|RT Builder. A list of Frontier Design distributors is available at Frontier Designs world wide web site, http//:www.frontierd.com.

Frontier Design will be demonstrating the A|RT Builder 1.5 and A|RT Library at the Design Automation and Test in Europe (DATE) conference, Booth D6, March 9 - 12, in Munich, Germany.

Frontier Design was founded in 1997 as the result of a management buy-out of the European Development Center of Mentor Graphics (NASDAQ: MENT). The firm's primary emphasis is its "algorithm-to-silicon" design methodology that greatly improves the creation of Silicon IP blocks starting from customer- proprietary or industry-standard algorithms in the fields of wireless telecom, consumer audio or multimedia applications. Algorithm-to-Silicon IP blocks consume less power, are less costly and require substantially less development time than other alternatives. Frontier Design sells its design services and a line of EDA tools directly from its facility in Leuven, Belgium, and from its sales office in California. Frontier Design also sells through a growing number of distributors and Value Added Resellers in Northern America, Europe, Japan and the Pacific Rim.

Frontier Design's World Wide Web site is http://www.frontierd.com. Email inquiries may be sent to [e-mail].

Note to Editors: Windows is a registered trademark of Microsoft Corporation. A|RT, Algorithm-to-Silicon and Algorithm-to-Register Transfer are trademarks of Frontier Design.