Frontier Design's Architectural Synthesis Methodology Triples Design Re-use Productivity; New Designs Take As Little As Half As Long To Complete.

LEUVEN, Belgium--(BUSINESS WIRE)--June 28, 1999--

Frontier Design announced its Interactive Architectural Synthesis Tool Kit at this year's Design Automation Conference in New Orleans.

The Architectural Synthesis Tool Kit allows the interactive synthesis of designs of 100,000 or more operations in half the time required for hand-coded HDL designs. Architectural synthesis can achieve die size, performance or power improvements of 50% to 90%, by facilitating broader and more extensive exploration.

The Architectural Synthesis Tool Kit is ideal for the development of architecture- optimized, re-usable designs and for the implementation of highly optimized systems on a chip (SoCs)

The interactive Architectural Synthesis Tool Kit consists of a variety of add-ons to Frontier's ART(TM) Builder C-to-HDL translation software. It is the culmination of more than a decade long EDA tool development effort at Frontier and its predecessor, the European Development Center (EDC). Together, ART Builder and the Architectural Synthesis Tool Kit completely eliminate the need to manually develop RT-level designs by providing a variety of automated paths from behavioral C-language models to RT-level descriptions and by providing comprehensive analysis and optimization tools.

Alpha tests of the Architectural Synthesis Tool Kit at Frontier's Design Centers have achieved significantly better optimization of silicon implementations. Initial designs have typically taken half as much design time as previously required to hand code them in Verilog or VHDL. The modification of existing designs for re-use have been completed in one-third the time required for HDL coding.

According to Herman Beke, Frontier Design's CEO, "Today, there are three synthesis steps that can help a designer to get his designs into silicon: logic synthesis, behavioral synthesis and, now, architectural synthesis. Both logic and behavioral synthesis require their own type of HDL-input. Logic synthesis optimizes results by minimizing redundant logic in the silicon. Although this approach can yield significant improvements, it does not give the designer any opportunity to improve the overall architecture, without re-writing and re-simulating the HDL - a process that is too difficult and time-consuming to be repeated very often.

"Behavioral synthesis, on the other hand, attempts to find the most optimized architecture for the design, based on a behavioral description. For small designs with less than a few hundred operations, it can be very effective. However, behavioral synthesis gives the designer very little freedom to drive the architecture in a given direction, and the number of possible solutions grows exponentially as the number of operations grows. The result is that the synthesis process can take hours or days for large designs and there is an increasing likelihood that the synthesized solution will bear little resemblance to what the designer had in mind.

"Like behavioral synthesis, architectural synthesis tries to find the best architecture for the design. However, since it is interactive, the designer has much more control over the outcome. The designer can pre-allocate resources for the design, assign some or all operations to those resources and specify resource sharing or scheduling. Since the designer has more control, the synthesis process is very quick, taking only a few minutes. The designer can explore multiple architectures until the best result is achieved. Architectural synthesis extends designer creativity as well as productivity. And since the design can stay in C, it is a truly re-usable design," Beke concluded.

There are a number of advantages to designing in the C-language. C is the lingua franca of system engineers, so there is better communication between the system and silicon designers if both use C. C simulation is at least an order of magnitude faster than HDL simulation, so designers can do multiple design iterations very quickly and simulate them more thoroughly. C-language designs are largely architecture-independent, whereas synthesizable HDL designs are, by definition, architecture-dependent. The architecture-dependency of HDL-level designs is a major obstacle to design re-use. Modifying an HDL design for re-use, requires and extensive or complete re-write. As a result, HDL designs are not all that re-usable. In contrast, designs done in C, can be quickly modified and simulated, so a previous design can be altered to work in a new system with minimal effort.

With architectural synthesis, a designer has much greater power to optimize a C-language design. Interactive architectural synthesis can be used to try various architectures until the most highly optimized implementation is found. Optimizing the architecture necessarily leads to greater improvements than just optimizing the logic.

In spite of the advantages of using the C-language, Verilog and VHDL are the languages of silicon design and, until the recent introduction of Frontier's "Algorithm-to-RTTM (ART) tools, the only way to get an RT-level design was to write it from scratch - a time-consuming process that isn't likely to be done more than once.

By extending the design flow from ART Builder to allow architectural optimization and synthesis, the Architectural Synthesis Tool Kit fosters the development of truly re-usable designs and will enable highly optimized systems-on-a-chip.

Frontier Design's European Design Services unit has been using an alpha version of the Architectural Synthesis Tool Kit internally for the synthesis of C-language IP blocks into silicon implementations for Frontier's design services customers. Koen Van Nieuwenhove, Frontier's Vice President of Technology, heads up the firm's European Design Centers. He says, "We have achieved enormous productivity gains by using the Architectural Synthesis Tool Kit. The designs we have done have taken about half as much time as they would take directly coding in an HDL.

For example, in just three months, we achieved a highly optimized silicon implementation of the G723.1 speech compression algorithm that's used for example in digital answering machines. The G723.1 algorithm requires about 600,000 operations per frame, and usually requires all the processing power of a TMS320C50 DSP core - or about 50,000 gates. By using the Architectural Synthesis Tool Kit to explore alternative architectures we arrived at a 25,000 gate silicon implementation with 25 Kbits of ROM that operates at just 20 MHz - a much more silicon efficient, lower power solution.

"Had we tried to code the algorithm in VHDL by hand, it would have taken at least six months, so we cut our design time in half.."

"More importantly," Van Nieuwenhove explained, "when the G723.1 standard was upgraded to G723.1A that includes silence as well as speech compression, we were able to use the original behavioral C-algorithm as the basis for the new design. The Architectural Synthesis Tool Kit allowed us to fix the available resources at 25,000 gates with 25 Kbits of ROM, so we didn't have to increase the resources. We could not have fixed the resources using a conventional behavioral synthesis tool. Even the slightest design modification would have caused a deviating architecture and would have required a completely new design.

"The new design was finished in just six weeks without adding any additional resources. Hand coding the design in VHDL or Verilog would have required a substantial re-design and would have taken about five months -- three times longer than required using the Architectural Synthesis Tool Kit. This result illustrates the beauty of interactive architectural synthesis," Van Nieuwenhove said. "Designs really are re-usable, the design cycle is shorter, and the designer is allowed to be creative in getting the best possible solution."

The tools will be commercially available in late 1999 and early 2000. Prices of Architectural Synthesis Tool Kit add-ons to ART Builder start at $45,000.

Frontier Design was founded in 1997 to develop a next generation system level design methodology called ART (Algorithm to Register Transfer) and to sell innovative EDA products and design services based on this methodology. ART EDA tools start from a specification in the C-language. They are used by Verilog or VHDL hardware designers to improve design productivity and design quality, in terms of product cost, power consumption and performance. The ART design methodology supports existing system-level design flows provided by companies such as Cadence Design Systems (NYSE: CDN), Mentor Graphics (NASDAQ: MENT), Synopsys (NASDAQ: SNPS), and by offering a quick and easy path from the C-language to Verilog or VHDL.

Frontier Design sells its tools and design services from its facilities in California; Florida; Leuven, Belgium; Tiel, The Netherlands; Tokyo, Japan; and through a growing number of distributors and representatives in North America, Europe, Japan, and the Pacific Rim.

Frontier Design's World Wide Web site is http://www.frontierd.com. Please email inquiries to [e-mail].