Fluence Technology Delivers New Pre-silicon Validation Software.

Business Editors, High-Tech Writers

International Test Conference

Booth 251

ATLANTIC CITY, N.J.--(BUSINESS WIRE)--Oct. 3, 2000

TDS SimValidator's New Direct Access Scan Option

Speeds Scan-based Simulation Time for Complex

System-On-Chip Designs

Fluence Technology Inc.(TM), a pioneer provider of integrated mixed-signal design and test automation solutions, today announced the TDS_SimValidator(TM) Direct-Access Scan (DAS) option enabling increased performance of scan-based simulation for large system-on-chip (SoC) designs.

This new capability brings a new level of efficiency to the design process by directly addressing the verification bottleneck that occurs when verifying tester data against a golden simulation environment.

Fluence's TDS_SimValidator allows designers to use simulation to confirm that the test vectors and timing specifications targeted to their automatic test equipment (ATE) are faithful to the device design specification. Now Fluence is extending pre-silicon, first-pass validation to scan-based design simulation through the DAS option of the TDS_SimValidator. In one clock cycle, the TDS-SimValidator's DAS option can generate scan shifts and validate the critical output scan state.

"In event-based simulation, processing one bit of scan data into and out of a scan chain generates a tremendous number of events to resolve for each scan clock cycle," said Mike Kondrat, vice president of marketing, Fluence Technology. "This becomes terribly expensive, time consuming and redundant because once a scan chain has been simulated once or twice, no new simulation behaviors are generated, therefore nothing new is validated."

"The TDS_SimValidator DAS mode overcomes this burden by applying all pattern data to all internal scan nodes at one time. This enables the validation of the `system clock' cycle between scans and the validation of the next scan output state which is critical to the test being performed," added Kondrat.

The TDS_SimValidator DAS mode validates the scan output state against the internal state of the design in one clock cycle. It also applies the next input scan state on the internal elements. By applying the next scan input data in one clock cycle, the simulation time necessary to validate the next test cycle is reduced by the number of scan elements in the scan chain. This is usually very large and the time saved is often over an order of magnitude. In other words, the larger the scan design, the larger the saving in simulation time when using TDS_SimValidator DAS mode. The TDS_SimValidator uses the Verilog Programmatic Language Interface (PLI) to access and drive the device model with the TDS Wave-form Data Base (WDB).

Pricing and Availability

The TDS_SimValidator is priced at $25,000 a seat. The Direct-Access Scan (DAS) mode is available immediately and is free to TDS_SimValidator customers who are on the Fluence TDS maintenance contract. The TDS_SimValidator and the DAS mode support Cadence Verilog-XL. Support for other popular simulators is planned. Supported platforms are Sun Solaris UNIX.

About Fluence Technology

Fluence Technology, formerly known as TSSI, is a leading provider of mixed-signal design and test automation software. Fluence provides an integrated development environment between ASIC, EDA and ATE suppliers. More than 250 of the world's top electronics companies reduce time-to-market by using Fluence's innovative products, services and support. Fluence, a wholly owned subsidiary of Credence Systems Corporation (Nasdaq:CMOS), has headquarters in Beaverton, Oregon, with sales offices and distributors throughout the world. Please visit the company's Web site at www.fluence.com or contact [e-mail] for more information.

Trademarks mentioned in this release are the intellectual property of their respective owners. (c)2000 Fluence. All rights reserved.