Flip chip underfill and flux residue with lead free: this study presents data on the compatibility of 17 different flux systems with two underfill systems in a lead-free flip chip assembly process.Worldwide, electronics manufacturers are investigating new lead-free alloys and their effects on the reflow (1) The process of heating and melting the solder that has been screen printed onto a printed circuit board in order to bond chips and other components to the board. Surface mount chips (SMT) use the reflow method. Contrast with wave soldering. See also reflowable text. process, an important first step in developing robust lead-free processes. Once lead-free processes are well developed, determining the effect of these changes on the various materials sets used in electronic assemblies is important. [TEXT NOT REPRODUCIBLE IN ASCII ASCII or American Standard Code for Information Interchange, a set of codes used to represent letters, numbers, a few symbols, and control characters. Originally designed for teletype operations, it has found wide application in computers. ] The leading lead-free alloy candidates are the different tin-silver-copper (Sn/Ag/Cu) formulations (often abbreviated as SAC) recommended by NEMI NEMI National Electronics Manufacturing Initiative NEMI National Environmental Methods Index (1) in the U.S. and IRTI IRTI Islamic Research and Training Institute in the European Union European Union (EU), name given since the ratification (Nov., 1993) of the Treaty of European Union, or Maastricht Treaty, to the European Community . (2) The Sn/Ag/Cu eutectic system has a melting point melting point, temperature at which a substance changes its state from solid to liquid. Under standard atmospheric pressure different pure crystalline solids will each melt at a different specific temperature; thus melting point is a characteristic of a substance and of 217[degrees]C, significantly higher than the 183[degrees]C melting point of eutectic tin/lead (Sn/Pb) alloy. These new alloys increase the peak reflow temperature from 220[degrees]C up to 240 or 260[degrees]C, a factor that affects material performance. This study deals with one aspect of lead-free processing for flip chip A chip packaging technique in which the active area of the chip is "flipped over" facing downward. Instead of facing up and bonded to the package leads with wires from the outside edges of the chip, any surface area of the flip chip can be used for interconnection, which is typically done in a package: flip-chip underfill adhesion to lead-free flux residues. [FIGURE 1 OMITTED] The interaction between the flux and the underfill is important for the long-term reliability of underfilled flip chip devices. (3), (4) All fluxes leave behind residues after reflow. When properly processed, no-clean or low-solid flux residues do not degrade electrical performance (such as with SIR and ECM (1) (Enterprise Change Management) See version control and configuration management. (2) (Error Correcting Mode) A Group 3 fax capability that can test for errors within a row of pixels and request retransmission. ) but will affect the adhesion and flow of the underfill. Elevated lead-free processing temperatures change the characteristics of the flux residues after reflow. [FIGURE 2 OMITTED] This study examines tacky fluxes for their ability to provide a reliable and consistent interconnect in a lead-free flip chip reflow process. After initial evaluation, parts were conditioned, and reliability was assessed to determine JEDEC The division of the Electronic Industries Alliance (EIA) that deals with semiconductor standards (officially, the JEDEC Solid State Technology Association of EIA). JEDEC was formed in 1958 when the Joint Electron Tube Engineering Council (JETEC) split into two Joint Electron Device level 3 with a 260[degrees]C reflow compatibility. The 260[degrees]C peak reflow temperature simulates the worst possible reflow conditions that a package can undergo in a surface-mount manufacturing process. Parts were then evaluated using scanning acoustic microscopy for evidence that the flux residues affected reliability (Figure 1). Flux residues can affect reliability in two different ways. Present on the solder bump, substrate or die, thin films of flux residue can significantly reduce interfacial adhesion between the flux and the surfaces. Once the underfilled device is stressed by thermal shock Thermal shock in mechanical models Thermal shock is the name given to cracking as a result of rapid temperature change. Glass and ceramic objects are particularly vulnerable to this form of failure, due to their low toughness, low thermal conductivity, and high , humidity or other factors, the underfill delaminates from the surface, and a gap can be detected using acoustic microscopy. [FIGURE 3 OMITTED] Fluxes can also affect reliability by physically impeding the flow of underfill material. Flux residue buildup in the gap between bumps or between the die and the substrate can narrow the gap to a point where the underfill cannot flow (Figure 2), or the edges flow faster, encapsulating air and creating a void. To ensure a void-free underfill, homogenous homogenous - homogeneous wetting of the underfill must occur on all surfaces. If wetting is not homogenous, voids in the uncured underfill may translate into reliability problems later. With the change to a lead-free reflow process, the characteristics of the flux residues change significantly. This study presents data and analysis on the compatibility of 17 different flux systems with two underfill systems in a lead-free flip chip assembly process. [FIGURE 4 OMITTED] Experimental The test component was a 14.4 X 14.4 mm flip chip with polyimide Pronounced "poly-ih-mid." A type of plastic (a synthetic polymeric resin) originally developed by DuPont that is very durable, easy to machine and can handle very high temperatures. Polyimide is also highly insulative and does not contaminate its surroundings (does not outgas). passivation passivation the final stage in instrument manufacture, passing the finished instruments through a bath of nitric acid which removes foreign particles and promotes the formation of a protective coating of chromium oxide. . The bump pattern was a full array of 3,840 bumps at a pitch of 225 [micro]m. Two lead-free alloys were used as bump metallurgy: Sn/3.5 Ag/0.5 Cu and Sn/3.0 Ag/1.0 Cu. The substrate was a four-layer BT laminate laminate, n a thin slice of porcelain or plastic fabricated in a dental lab, which is cemented to the front of the teeth to cover gaps, whiten stained teeth, or reshape chipped or broken teeth. at a thickness of 1 mm. The solder mask An insulating pattern applied to a printed circuit board that exposes only the areas to be soldered. was PSR PSR Pulsar PSR Poster PSR Physicians for Social Responsibility PSR Psychosocial Rehabilitation PSR Pacific School of Religion PSR Policy and Survey Research PSR Project Study Report PSR Pre-Sentence Report PSR Pressure-State-Response PSR Puget Sound Region 4000 AUS AUS abbr. Army of the United States 5, and the surface finish on the pads was electroless nickel/immersion gold (ENIG ENIG Electroless Nickel Immersion Gold (printed circuit board manufacturing process) ). The assembly was performed using the following procedure. The flip chips were dipped into a flux pot with a dip/coating height set to 50 microns and placed using an SEC Model 850. The parts were then reflowed using a BTU Btu: see British thermal unit. Paragon 150, under nitrogen (less than 30 ppm [O.sub.2]) using a lead-free profile with a peak temp of 245[degrees]C (Figure 3). After reflow, the devices were underfilled with either of two underfills (Table 1) using an Asymtek C270 automated dispenser. Both underfills were treated to the same cure cycle: ramp to 165[degrees]C over one hour, then held at 165[degrees]C for one hour. After curing, a Sonoscan D6000 scanning acoustic microscope Please help recruit one or [ improve this article] yourself. See the talk page for details. imaged all parts using a 100 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. transducer transducer, device that accepts an input of energy in one form and produces an output of energy in some other form, with a known, fixed relationship between the input and output. (time 0 scans). At this point, some parts were set aside for cross-sectioning to measure the die to substrate gap. After recording the initial acoustic images, the parts were conditioned as per JEDEC level 3 testing (Table 2). Parts were baked at 125[degrees]C for 24 hours Adv. 1. for 24 hours - without stopping; "she worked around the clock" around the clock, round the clock to establish the same moisture level baseline for all parts, then conditioned for 192 hours at 30[degrees]C/60% relative humidity relative humidity n. The ratio of the amount of water vapor in the air at a specific temperature to the maximum amount that the air could hold at that temperature, expressed as a percentage. (RH), as per the J-STD-022. After conditioning, the parts were subjected to three lead-free reflows with a peak temperature of 260[degrees]C (Figure 4) and imaged again using the acoustic microscope. [FIGURE 5 OMITTED] Results Initial Wetting Wetting and gap height were measured on select samples. When the flux system worked properly, the solder bump melted and wetted out along the pad, the package collapsed, and the overall gap height was reduced. Based on gap heights, fluxes were designated with performances of good, fair or failure. Failures correspond to a lack of connection between the flip chip and the substrate pads. A summary of the results is presented in Table 3. [FIGURE 6 OMITTED] Solder joints were evaluated over three separate builds. Since slight variations occurred in the solder mask definition, the gap heights were only comparable within a column. Other criteria used to evaluate soldering performance were wetting to the pad, bump shape after collapse and overall solder joint appearance. [FIGURE 8 OMITTED] Most fluxes met the requirements of lead-free reflow of flip chips in a nitrogen environment. Figure 5 shows a good solder joint with good wetting along the pad and a collapsed bump. Figure 6 illustrates a fair solder joint with poor wetting to the pad. The worst performer did not form a solder connection at all--when the part was underfilled and cured, the device floated (Figure 7). [FIGURE 7 OMITTED] All parts, except the ones assembled with the flux that did not allow reflow, were placed into the next segment of the testing. JEDEC Level 3/260[degrees]C Reliability This study used JEDEC testing to determine flux residue/underfill compatibility. With flux residue compatibility, moisture conditioning and subsequent thermal treatment Thermal treatment is a term given to any waste treatment technology that involves high temperatures in the processing of the waste feedstock. This commonly, although not exclusively involves the combustion of waste materials. can force a failure when moisture intrudes where the underfill does not adhere well to the flux residue. As flux residues may be slightly hygroscopic hygroscopic /hy·gro·scop·ic/ (hi?gro-skop´ik) readily absorbing moisture. hy·gro·scop·ic adj. Readily absorbing moisture, as from the atmosphere. , any moisture that does penetrate an exposed flux surface can be absorbed. This condition is exacerbated when poor adhesion occurs between the underfill and the flux residues. [FIGURE 9 OMITTED] After exposure to moisture conditioning, the parts were reflowed three times with a peak temp of 260[degrees]C. During reflow, any absorbed moisture within the part expands (popcorning), creating the voids observed in the acoustic microscopy images (Figure 8). A summary of all the flux/underfill systems examined and their performance are presented in Table 4. Out of all the fluxes examined, only two were incompatible with both underfill systems (Figure 9). Four fluxes exhibited excellent performance characteristics with both underfills (Figure 10). Most of the fluxes were compatible only with Underfill System B. One proprietary epoxy flux system showed better performance with Underfill A over Underfill B. [FIGURE 10 OMITTED] Conclusions This study evaluated a number of material sets for lead-free processes. The tacky flux and underfill systems are designed for the flip chip packaging process. The movement to a lead-free process affects the moisture level rating of packages and devices. (5) One of the materials that impacts this JEDEC moisture level rating is the underfill. This study shows that some flux residue/underfill systems are suitable for lead-free processes. Flux Systems G, L, N, and P are more compatible to different underfill material sets than others. Underfill System B, developed with a chemistry specifically designed to interact with flux residues (6) and meet JEDEC level 3/260[degrees]C requirements, shows excellent compatibility with almost all the flux residues.
TABLE 1: Underfill systems used in lead-free flux evaluation.
Property UF A UF B
Curative Anhydride Anhydride
Filler 42% (silica) 64% (silica)
CTE ([[alpha].sub.1]) 44 22
[T.sub.9] 140 120
TABLE 2: JEDEC pre-conditioning environment as per J-STD 022A.
Level Time Conditions
1 168 85[degrees]C / 85% RH
2 168 85[degrees]C / 60% RH
2a 696 30[degrees]C / 60% RH
3 192 30[degrees]C / 60% RH
4 96 30[degrees]C / 60% RH
5 72 30[degrees]C / 60% RH
5a 48 30[degrees]C / 60% RH
6 TOL 30[degrees]C / 60% RH
TABLE 3: Initial solder joint evaluation.
Run 1 Run 2
Flux Underfill Gap Joint Underfill Gap Joint Quality
([micro]m) Quality ([micro]m)
A
B 70 Good 77 Good
C 73 Good 83 Good
D 91 Excess Flow
E 83 Good
F 77 Fair 102 No Connection
G 76 Fair 81 Good
H 66 Good 81 Good
I 86 Poor
J 83 Good
K
L 80
M 81 Good
N 83 Good
O 83 Good
P
Q 77 Fair 84 Good
Run 3
Flux Underfill Gap Joint Quality
([micro]m)
A 60 Good
B 63 Good
C 64 Good
D
E 60 Good
F 108 No Connection
G 62 Good
H
I
J 63 Good
K 65 Good
L 63 Good
M 65 Good
N 64 Good
O
P 61 Good
Q
TABLE 4: Summary of flux/underfill performance.
Flux Joint Performance Performance Overall
Quality with UF A with UF B Performance
A Good Good Fair UF A only
B Good Poor Good UF B only
C Good Poor Good UF B only
D Poor Poor Poor Poor
E Good Fair Good UF B only
G Good Good Good Excellent
H Good Poor Poor Poor
I Poor Poor Good UF B only
J Good Poor Good UF B only
K Good Poor Good UF B only
L Good Good Good Excellent
M Good Poor Good UF B only
N Good Good Good Excellent
O Good Poor Good UF B only
P Good Good Good Excellent
Q Good Fair Good UF B only
Acknowledgment: The authors would like to acknowledge Tom White for his assistance. References (1.) C. Handwerker, "NEMI Pb-free Solder Project," Proc. Technical Program SMTA SMTA Surface Mount Technology Association SMTA Standard Material Transfer Agreement SMTA Subordinate Message Transfer Agent SMTA Sewing Machine Trade Association (UK) SMTA Sekolah Menengah Tingkat Atas International, 2003. (2.) www.npl.co.uk/ei/news/pbfree.html. (3.) G. Carson and M.E. Edwards, "Factors Affecting Voiding in Underfilled Flip Chip Assemblies," Proc. Technical Program, SMTA International, 2001. (4.) P.N. Houston, et al., "Low Cost Flip Chip Processing and Reliability of Fast-Flow, Snap-Cure Underfills," Proc. Technical Program, ECTC ECTC Electronic Components and Technology Conference ECTC Erosion Control Technology Council ECTC Earth Commission for Thermostatic Control (from environmentalist book The Weather Makers) ECTC Expected Cost to Company , 1999. (5.) M. Kwoka and G. O'Brien, "Pb-free skunk skunk, name for several related New World mammals of the weasel family, characterized by their conspicuous black and white markings and use of a strong, highly offensive odor for defense. works project," IPC (1) (InterProcess Communication) The exchange of data between one program and another either within the same computer or over a network. It implies a protocol that guarantees a response to a request. APEX, 2000. (6.) Flux chemistry and compatibility presented at SMTA International, September 2004. Brian J. Toleno, Ph.D., and George Carson, Ph.D. Brian J. Toleno, Ph.D., is senior applications chemist--assembly materials; email: brian.toleno@henkel.com; and George Carson, Ph.D., is director of application engineering--packaging materials; email: george.carson@henkel.com--both with Henkel Corp., Industry, CA. |
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