FishTail and Mentor Graphics Collaborate on False Path Verification Flow.

FishTail's Refocus Product Interfaces with Mentor's FastScan and TestKompress Products to Exhaustively Verify False-Paths at the Gate-Level

PORTLAND, Ore. -- FishTail Design Automation, Inc., the golden timing constraints company, today announced that it has worked with Mentor Graphics to put in place a methodology for exhaustively verifying false paths at the gate-level.

In the new flow, FishTail's constraint management product Refocus[TM] is used to generate an exhaustive list of all the paths in a gate-level netlist that are made false by the false-path definitions in a Synopsys Design Constraint (SDC) file. The SDC file provided as input to Refocus may describe false paths at either the gate-level or RTL. The SDC file may have been created by designers manually or automatically generated by FishTail's timing-exception generation product Focus[TM]. The path report generated by Refocus is provided as input to Mentor Graphics' automatic test pattern generation (ATPG) products, FastScan[TM] or TestKompress[R]. Mentor's ATPG products then use the embedded critical path ATPG engine to identify if any of the paths in the Refocus path report can be sensitized. No stimulus is required to perform this exhaustive analysis, nor is it necessary for the netlist to have scan insertion performed on it. If the FastScan or TestKompress products confirm that all paths cannot be sensitized, designers can move forward with using their SDC file in the chip-implementation flow secure in the knowledge that their false-path definitions have been exhaustively proven to be correct.

"FishTail's Confirm[TM] product is used by customers worldwide to formally verify timing exceptions at the RT level," stated Ajay Daga, founder and CEO of FishTail. "The gate-level verification of false paths is important to our customers and so is the ability to verify Focus generated false paths using third-party tools. We are committed to building interfaces with proven and mature products that customers already own to verify timing exceptions. Our integration with Mentor's test pattern generation products is a part of this commitment and will be of immediate benefit to the design community."

"FishTail's false path verification flow with Mentor Graphics ATPG products provides a new and innovative way for customers to use our products," said Greg Aldrich, Director of Marketing, Design-for-Test product line, Mentor Graphics. "Verifying design constraints can be a difficult task for design teams and false path verification is something that the FastScan and TestKompress products are particularly well suited for."

About FishTail Design Automation

Founded in 2002, FishTail Design Automation has set its sights on tackling the difficult problem of precise constraints on chip timing - the area where the success or failure of a design is ultimately determined. The company's patented technology improves chip implementation by automatically generating and verifying exceptions to single-cycle clocking from RTL and netlist descriptions. FishTail is privately funded. For more information about FishTail, please visit the company's website at www.fishtail-da.com.