Finding the short: a transistor was failing. What was the cause?

A dual die transistor was shorting between pins 1 and 2 and between pins 4 and 5, (source and gate on both die, Figure 1). Shorts between pins 1 and 6 and pins 2 and 6 were present (source and drain and gate and drain on die 1). The drains are located at pins 3 and 6.

Test methods. The failed transistor was removed from the assembly along with a tape section of good components. The pin--to-pin I-V characteristics for the failed and good transistors were confirmed with a curve tracer. The good and failed transistors were soldered upside down (based on the components' wire-bonding, which was bottom-side, per Figure 1) onto HASL-coated copper coupons. They were then decapsulated using a controlled combination of fuming nitric and fuming sulfuric acid. The decapsulated components were examined optically and by SEM to determine evidence of the failure mode and mechanism.

Results

* Based on the component circuit diagram (technical data sheets), the substrate is tied to the source lead.

* Based on x-ray imaging, the wire bonds were oriented from underneath (Figure 1).

[FIGURE 1 OMITTED]

* Curve tracer analysis indicated a short between the gate and source, drain and gate, and source and gate on die 1. Die 2 showed a short between source and gate and drain and gate. Drain and source curves for die 2 appeared typical.

* The drains, gates and sources are identified in Figure 2.

[FIGURE 2 OMITTED]

* Residual degraded encapsulant was present after extensive decapsulating steps, indicating the material in this area was taken past its Tg (glass transition temperature), which is evidence of a thermal excursion (Figures 3 and 4).

[FIGURE 3 OMITTED]

[FIGURE 4 OMITTED]

* It was difficult to determine the presence of a specific failure mechanism (i.e., flash-over) because of the degraded residual encapsulant. However, die 1 appears stressed based on the cracked or wishbone appearance in the insulator layer areas where the degraded encapsulant resided (Figures 5 and 6).

[FIGURE 5 OMITTED]

[FIGURE 6 OMITTED]

Conclusions and recommendations. The shorts observed on the transistors are the result of an electrical overstress (EOS), most likely an overcurrent scenario as indicated by damage observed on the failed transistor. The cause of the EOS could be from a number of the following:

1. Use of the component outside of its recommended specifications.

2. No current limiting designed into the board to prevent a circuit load from damaging the assembly.

3. Transient voltages in the circuit that could cause short durations of currents above specifications.

The encapsulant degradation suggests an overcurrent scenario over an extended period of time.

As part of failure mode analysis, we recommend examining the circuit application for possible sources of overvoltage and overcurrent. In addition, a review of the specification requirements/limits for the transistor in this circuit is recommended.

The American Competitiveness Institute (aciusa.org) is a scientific research corporation dedicated to the advancement of electronics manufacturing processes and materials for the Department of Defense and industry. This column appears monthly.