Fabrication guidelines for backdrilling: for higher designs and thick boards backdrilling--the removal of plating from the unused portion of the via--reduces via capacitance and mitigates resonance.

Ed.: To see the entire article, including design guidelines, visit pcdandm.com/pcdmag/rnag/0311/11cohen.pdf.

Backdrilling, or controlled-depth counter boring, is a process in which plating is removed from the unused portion of the via. Multilayer circuit boards are processed conventionally, with a secondary drill operation added after plating, using CNC drilling equipment with controlled depth enhancements. CNC drill files permit this process to be automated and repeatable.

One important parameter is the secondary drill diameter. This drill diameter must be greater in diameter than the primary drill, to permit removal of all the electrodeposited plated metal--typically copper with an additional surface finish. It is important to minimize this diameter in order to avoid reduction of routing channels, which otherwise could compromise hole-to-trace spacing in the pin fields.

In a controlled experiment, Teradyne varied the over drill diameter to 0.005", 0,007", 0.010" and 0.013" greater than the original drill size to determine the presence of residual plating. Ten holes from each corner of four panels drilled on four spindles in one pass were cross-sectioned and evaluated for complete plating removal and internal spacing. To summarize the findings, no residual plating or spacing violations were observed on any over drill hole size. Teradyne's current recommendation is 0.007" over original drill diameter.

Backdrilling is a tradeoff between manufacturing cost and electrical performance. Contributors to backdrill depth variation have been characterized which affect yield and cost. Teradyne's optimized setup process achieves a 3 sigma overall variation of +/-0.005" to nominal target depth. This comes from two components: mechanical depth and layer position. It is recommended that at least a 0.010--target nominal depth be achieved before the last layer connected.

The Findings

A forced failure designed experiment was conducted, intentionally varying process parameters, taking the PTH integrity to extremes. The varied parameters were drilled hole quality,

electroless copper etchback rate and copper plating thickness. Test vehicles were subjected to thermal cycling and 6x solder shock testing. No failures were observed on either standard PTHs or backdrilled PTHs on boards processed under standard conditions. Failures due to cracking were observed on both hole types exhibiting poor drilled-hole quality and thin copper plating conditions (TABLE 1).

[FIGURE 1 OMITTED]

A cost model developed at Teradyne factors in setup time, run time and drill bit cost. Applied to various board designs, the average increase to the bare board price was 7%. For example, a typical board requiring 1,500 backdrilled holes would result in an additional cost of about $50 per board (TABLE 3).

Recommendations for surface finishes and exposed copper include:

* Backdrill after electrolytic deposition of surface finishes (reflowed tin-lead, gold), resulting in exposed copper at the end of the stub.

* Backdrilling can be done before immersion surface finishes, resulting in no exposed bare copper at the end of the stub.

* Immersion tin for backdrilled backplanes is preferred.

Assembly Reliability Tests

To evaluate backdrilled via structures, various reliability testing sequences applicable to PCB vias were performed in accordance with Telcordia GR-1217-Core and GR-2969Core requirements for telecommunications hardware. The test plan includes bare board sequences and testing to evaluate press-fit termination. This testing has been performed to quality level III. Temperature rise and solder shock testing was also performed. Vias were evaluated both with and without anchoring pads at the bottom of the plated hole or backdrilled end of the via. The Telcordia test vehicle was an 8 x 10", 26-layer FR-4 board, 0.260" thick, with hole sizes of 0.018" and 0.022".

The reliability test groups chosen to assess plated through-hole integrity were:

1. Compliant pin performance.

2. Current rating.

3. DWV dielectric withstanding voltage.

4 6. Humidity cycling and thermal shock.

7. Mixed flowing gas.

8. Electromigration.

[FIGURE 2 OMITTED]

[FIGURE 3 OMITTED]

[FIGURE 4 OMITTED]

The humidity cycling and thermal shock group was chosen to evaluate the effects of thermally stressing the via structure, in order to look for delamination between the copper plating and drilled hole. The mixed flowing gas group was performed to accelerate the corrosion rate between the compliant pin interface and PTH. The electromigration group analyzed the metallic material growth between the PTH and exposed copper layers. The compliant pin performance test mechanically stressed the via structure and evaluated the performance of the compliant pin. The purpose of mechanically stressing the via structure was to see if the copper hole would &laminate from the drilled hole wall. A portion of that particular group was also tested to failure, meaning that the pins were purposely pushed through the hole to try to cause the copper to & laminate.

Because backdrilling removes copper from the via, the current rating of the via was also tested to evaluate the current capacity. All the test vehicles had two different via structures, one with anchoring pads and the other without, to evaluate the mechanical stability of the via structure. Groups 1 and 4 to 6 also had three compliant pin repairs prior to submitting to testing.

The results of the testing are shown in FIGURES 1 to 7.

* Compliant pin performance testing showed no adverse effects on the backdrilled hole after three insertions and retentions.

* 88 insertion data points.

* 66 retention data points.

Electromigration testing was performed at 500 hrs., 10V bias. Bellcure requires 1,000 M[ohm] min. The results are at 15,000 M[ohm]. * 500 hrs., 10 V bias

* Spec. requirement: Bellcore 1000 M[ohm] min.

* Results: 15,000 M[ohm]

[FIGURE 5 OMITTED]

As shown, all groups passed testing per stated requirements. The groups all passed without the aforementioned anchor pads. Group 9 also passed, although the intent for this configuration was to stress the hole and not to imply this configuration be used in application.

[FIGURE 6 OMITTED]

In addition, Group 9 was subjected to solder shock per IPC-TM-650, overpinning and reverse pinning. No evidence of delamination at the interface of the PTH or backdrilled holes was found during either overpinning (FIGURE 8) or destructive test (FIGURE 9).

[FIGURE 7 OMITTED]

[FIGURE 8 OMITTED]

[FIGURE 9 OMITTED]

Backdrilling is being used in production to tune the characteristics of a PTH. The decision of when to backdrill depends primarily on the signal frequency content and the length of the stub. Although efforts to reduce stub effect can be accomplished through techniques such as using lower dielectric material to Reduce thickness or routing high speed signals to the bottom of the board, higher frequency designs and increased board thickness will force some treatment of the stub. It is also important to remember that the package or connector is critical to the signal path but independent of the stub effect, and for this reason changing the termination from press-fit to SMT may not resolve the inherent stub induced signal loss.

TABLE 1. Backdrilling Dimensional Configurations

ATTRIBUTE                                    CONNECTOR TYPE
                                             VHDM or VHDM-HSD   GbX
Drilled hole size                            0.026"             0.0225"
Recommended back drill diameter              0.033"             0.0292"
Power/ground plane antipad                   0.052"             0.046"
Nominal spacing plane to BD hole edge        0.013"             0.012"
Innerlayer pad size (1 oz. Cu, 0.001" A/R)   0.038"             0.035"
Outerlayer pad size                          0.049"             0.045"
Adjusted outerlayer pad                      0.030"             0.026"

Note: Values are typical. Deviations based an design are not uncommon.

Conclusion: Target Diameter=0.007" over drill diameter

TABLE 2. Design of Experiment

VARIABLE                    SET POINT
Plated copper thickness   High       Low
Drilled hole quality      Smooth     Rough
Etchback                  Positive   Negative

TABLE 3. Backdrilling Costing Example

ATTRIBUTE                    EX.1     EX. 2    EX. 3
PCB thickness                0.250"   0.300"   0.350"
Layer Count                  20       30       40
Depth 1/hole count           500      1,000    3,000
Depth 2/hole count           0        500      2,000
Depth 3/hole count           0        0        1,000
Rough PCB price              $500     $750     $1,500
Backdrilling charge          $30      $50      $140
Backdrilling cost increase   6%       7%       9%

Note: Assumes all boards are FR-4 material

ACKNOWLEDGEMENTS

A special thanks to Marc Cartier, Trent Do, Bill Kenny Mark Gailus, Joe Quimby, and Dave Anderson.

BIBLIOGRAPHY

Brian Wadell, Transmission Line Design Handbook, Artech House, 1991.

Ed.--This is adapted from a presentation titled "Practical Guidelines for the Implementation of Back Drilling Plated Through Hole Vias in Multi-gigabit Board Applications," from DesignCon East, July 2003, and is used with permission of the author.

TOM COHEN is a principle mechanical engineer in the New Product Development group at Teradyne (teradyne.com/tcs). His activities include the design and analysis of high-speed next-generation products.

IMPLEMENTATION RECOMMENDATIONS

1. Optimize pattern.

* Reduce crosstalk in footprint by alternating backdrilled vias.

* Match long trace lengths with shortest via stub

2. Establish zones to minimize number of backdrill depths.

3. Remove nonfunctional pads.

4. Creative routing and netlist design can remove layers and minimize via stub effects by thinning the boards.