FPGA-on-board design: the secret lies in optimizing pin assignments with concurrent, bi-directional tool flows.

In design environments today, there is a widening communication gap between the PCB design teams and FPGA design teams. Because of this, companies miss out on significant system performance gains. The resulting unpredictable design schedules imply unacceptable product slippages, which could result in unrealized business in the long run. The drive for more capacity, complexity and functionality makes the need for FPGA-on-board techniques especially critical now.

It is not a rare occurrence that an FPGA designer makes I/O pin assignments that are suboptimal for FPGA logic placement, based on preconceived notions that all I/O paths have critical timing, or based on arbitrary guidelines from the PCB design team. The two teams should negotiate the best pin assignments that would benefit both PCB and FPGA implementation. The FPGA performance gains can result in cheaper silicon, shorter design cycle time and, most importantly, faster time to market for product success.

So how is it possible to increase performance just by moving pins around? Today's FPGA designers suffer the same dilemma experienced by ASIC designers in the 1990s: interconnect is the dominant factor in propagation delays, sometimes accounting for 80% of overall critical path delay. Moving pins closer to their corresponding logic comprises the first step towards reducing interconnect delay. Consider the FPGA design floorplan diagram in FIGURE 1, which shows how the placement of I/O results in longer interconnect delays (long red lines).

[FIGURE 1 OMITTED]

Secondly, FPGAs contain registers in their I/O pad cells. FPGA designers often automatically optimize I/O paths by registering all paths to and from the chip, and placing those registers in the I/O pad cells. This usually conflicts with the very aggressive internal clock speeds, making it challenging to get data from the I/O pads into the chip at full speed. Some applications have the luxury of pipelining I/O in the FPGA to increase frequency by effectively allowing more distance between I/O pads and their corresponding logic, but many do not. What FPGA designers don't realize is that there may be slack available outside the chip to help their cause.

Why haven't FPGA designers tried to negotiate for greater flexibility in their I/O pin assignments? So far there hasn't been an effective framework, especially in terms of communicating that need to their colleagues on the PCB design team. Designers typically use board layout tools very early in the design cycle to assign pins, often before they have RTL code. FPGA synthesis enters into the flow only after a sufficient amount of the RTL code is finished for trial implementations. In particular, the interactive physical optimization features of the synthesis tool are typically used very late in the FPGA design cycle to address complex timing closure issues, sometimes through placement optimization.

Combining the features of these two hitherto separate design tool flows benefits both sides, since the design team can use the board layout features to adjust pin assignments and improve the FPGA placement, and invoke the synthesis tool to physically optimize a design based on the new pin assignments.

The typical use of this flow to optimize pin assignments is illustrated in FIGURE 2. In this example, the flow depicts the use of FPGA physical synthesis tools, PCB design tools or spreadsheets to assign FPGA pins, and place-and-route tools offered by the FPGA device vendors. The flow is divided into a setup phase and an iteration phase. During the setup phase (shown on the left):

[FIGURE 2 OMITTED]

* The FPGA RTL description is used to assign the top-level pins in board layout.

* The RTL is synthesized.

* A place-and-route run generates an initial placement.

Then the placed design is automatically read into the synthesis tool with back-annotated timing for analysis. In the iteration phase:

* The I/O placement and timing are analyzed in the synthesis tool.

* I/O pins are optionally adjusted in the board layout tool, and then placement is re-analyzed in synthesis using interactive, physically aware optimizations.

* Once pin assignments are final, another place-and-route run generates the device pinout report for PCB design.

Be careful when choosing a synthesis tool. This can be the key differentiator at this stage, as it not only significantly shortens the time needed for each of the iterations, but also reduces the total number of iterations, by allowing synthesis to be skipped when only I/O locations change, and reusing placement to speed place-and-route.

Design Schedule Impact

To maximize this flow's usefulness, it helps to consider the design schedule impact. Obviously, the lifespan of the design flow depends on the overall product schedule. For effective use of the board layout and I/O pin optimization tool, most pins must be unlocked so that they can move according to FPGA logic placement. For effective use of the synthesis tool features, a significant portion of the design must be completed to provide a realistic interplay between I/O pin assignments and core logic. These conditions often have little overlap, leaving little time to optimize I/O pad locations as indicated by the "optimize pinouts" phase in FIGURE 3.

[FIGURE 3 OMITTED]

The overall project schedules are impacted depending on tool usage, as described below.

The maximum effectiveness of this flow is achieved when the FPGA team can fully implement a design with no pin assignment constraints. This implies that the PCB does not go to final layout until both PCB and FPGA design teams are confident that the I/O pin assignments will not cause timing problems. This is illustrated in FIGURE 4.

[FIGURE 4 OMITTED]

Place-and-route does the initial pin assignments to give the best logic placement. But if timing problems arise due to poor I/O placement, I/O assignments are adjusted. Here's where the benefit of the integrated flow kicks in. The synthesis tool will not re-assign I/Os; instead, the I/O pin re-assignment is best handled by the board layout tool. Once finished, the final pin assignments are imported to the board layout tool for safe keeping, with full access to the PCB design team, which immediately continues with the design. In reality, the final FPGA implementation is achieved much after PCB layout, eliminating the possibility of moving pins at that time. But if a significant amount of RTL can be built--preferably those portions that have the greatest connectivity with I/O--then most of the FPGA timing issues related to poor I/O placement can be eliminated. Sometimes PCB respins offer an opportunity to move a few I/O pins. With advance notice, the FPGA designer can use this flow to assess possible pin moves to improve timing.

Minimum Effectiveness

The flow that results in the minimal effectiveness on design schedules has PCB netlists finished and ready for layout before designs begin. This implies that device pin assignments are due before FPGA designs begin, so the teams are forced to anticipate the top-level I/O assignments and reserve spares for future expansion. This is illustrated in FIGURE 5. This environment represents the minimum usefulness for this flow because it considers almost no logic placement.

[FIGURE 5 OMITTED]

Board layout tools that effectively handle I/O pin assignment, as well as FPGA design tools that provide advanced automatic and interactive synthesis techniques, clearly play important individual roles within two separate--and equally important--processes in FPGA-based system designs. However, the "toss it over the wall" attitude prevalent within FPGA and PCB design must change. Optimal I/O pin assignments rarely happen in a vacuum.

As the capacities and complexities of new FPGA devices with higher pin counts continue to grow, the challenges and overall project costs begin to escalate out of control, which to a certain extent can be attributed to the growing number of increasingly prolonged FPGA-PCB iterations. The key to addressing these challenges--and speeding time-to-market--is an integrated, concurrent FPGA flow that bridges the communication gap between PCB and FPGA design teams.

RON PLYLER is a technical marketing engineer at Mentor Graphics; [e-mail].