Elpida Memory's 512 Megabit DDR400 SDRAM Devices Enable High-Speed, 1 Gigabyte Memory Modules for Desktop and Workstation Computing.Business Editors/High-Tech Writers TOKYO--(BUSINESS WIRE)--Aug. 25, 2003 Improved Low Latency Clock Cycles Match Processor Speeds to Provide Maximum System Performance Elpida Memory, Inc. (Elpida), an industry-leading provider of Dynamic Random Access Memory Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. (DRAM), today announced the availability of its 512 Megabit DDR400 SDRAM (Synchronous DRAM) A type of dynamic RAM (DRAM) memory chip that has been widely used since the late 1990s. SDRAM chips eliminated wait states by dividing the chip into two cell blocks and interleaving data between them. components and its 1 Gigabyte unbuffered dual in-line memory modules (DIMMs) designed for high-density, high-speed performance in desktop and workstation applications. Within the computing industry, DDR400 memory is considered to be an important architecture for achieving maximum system performance because it allows the microprocessor's front-side bus and the memory to be synchronized at the very high data rate of 400 Megabits per second (unit) megabits per second - (Mbps, Mb/s) Millions of bits per second. A unit of data rate. 1 Mb/s = 1,000,000 bits per second (not 1,048,576). E.g. Ethernet can carry 10 Mbps. (Mbps) per pin. On a 1 Gigabyte module, this translates to 3200 megabytes per second (unit) megabytes per second - (MBps, MB/s) Millions of bytes per second. A unit of data rate. 1 MB/s = 1,000,000 bytes per second (not 1,048,576). (PC3200). "High-performance computers will really benefit from the lower latency products because of their ability to decrease memory access clock cycles," said Jun Kitano, director of Technical Marketing for Elpida Memory. "Elpida's DDR400 devices and modules combine both high-frequency and low latency operation to create an optimal environment for robust system performance." 512 Megabit DDR400 SDRAM Components Elpida's new 512 Megabit SDRAM devices (Part number: EDD5108ADTA ADTA American Dance Therapy Association. ADTA, n.pr See American Dance Therapy Association. ) are manufactured using Elpida's proven 0.11 micron process technology at its state-of-the-art 300 mm fabrication facility in Hiroshima, Japan. The devices operate at 200 MHz and they are organized as 64 Million words x 8-bits in TSOP packages. Elpida's devices now achieve a low latency of both (3-3-3) and (3-4-4). These three numbers, commonly referred to as the JEDEC speed bin, are defined as CAS latency (CL), RAS (1) See network access server. (2) (Remote Access Service) A Windows NT/2000 Server feature that allows remote users access to the network from their Windows laptops or desktops via modem. See RRAS and network access server. to CAS Delay (tRCD), and Row Precharge (tRP), thus (CL=3-tRCD=3-tRP=3). The lower latency, (3-3-3) and (3-4-4) devices increase system performance by shortening the total clock cycles necessary for memory access including access time, array activation and precharge. 1 Gigabyte Unbuffered DDR DIMMs Based on Elpida's newest DDR400 devices, the JEDEC-standard, 184-pin 1 Gigabyte PC3200 modules (Part numbers: EBD EBD Emotional or behavioral disorder 11UD8ADFB, EBD11ED8ADFB) are organized as 128 Million words x 64/72-bits x 2 ranks), and enable low-voltage (VDD 2.6 V +/- 0.1 V) operation. The DIMMs transfer data at a rate of 3200 Megabytes per second, and they have a programmable CAS latency (CL) of 3, and a burst length of 2, 4, 8. The modules are unbuffered for PC and workstation applications, and they are composed of 16 high-performance 512 Megabit x8 DDR400 components. The module is also available in an unbuffered, x72 configuration that supports Error Correction Code Noun 1. error correction code - (telecommunication) a coding system that incorporates extra parity bits in order to detect errors ECC telecommunication - (often plural) the branch of electrical engineering concerned with the technology of electronic (ECC (1) (Error-Correcting Code) A type of memory that corrects errors on the fly. See ECC memory. (2) (Elliptic Curve Cryptography) A public key cryptography method that provides fast decryption and digital signature processing. ) for high-end workstation applications. About Elpida Memory, Inc. Elpida Memory, Inc. is a manufacturer of Dynamic Random Access Memory (DRAM) with headquarters based in Tokyo, Japan, and sales and marketing operations located in Japan, North America, Europe and Asia. Elpida offers a broad range of leading-edge DRAM products. Elpida is a joint venture company formed by NEC (NEC Corporation, Tokyo, www.nec.com, www.necus.com) An electronics conglomerate known in the U.S. for its monitors. In Japan, it had the lion's share of the PC market until the late 1990s (see PC 98). NEC was founded in Tokyo in 1899 as Nippon Electric Company, Ltd. and Hitachi on Dec. 20, 1999 and has been in operation since April 2000. For more information, visit www.elpida.com. All trademarks are the property of their respective owners. Reader Contacts www.elpida.com Elpida Memory, Inc. 2-1 Yaesu 2-Chome, Chuo-ku Tokyo, Japan 104-0028 Tel: 81-3-3281-1606 www.elpida.com Elpida Memory (Europe) GmbH. Grafenberger Allee 136 40237 Duesseldorf, Germany www.elpida.com Elpida Memory (USA) Inc. 2001 Walsh Avenue Santa Clara, CA 95050 Tel: 408-970-6600 Fax: 408-970-6999 info@elpida.com |
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