Effects of plane splits on high-speed signals, Part 2: signal and power integrity degradation can occur in PCBs and IC packages due to high-speed traces traversing plane-splits.

THE PROPER ANALYSIS and design of current return path for high-speed PCBs can be critical for achieving optimum system performance. The return current loop is often unclear from design's schematic drawing (10), which mainly illustrates electrical connections of circuit components or signal flow. The return current is influenced by board layout, stackup, via transitions (11), connectors and voids/ splits in reference ground/power layers. For instance, the stackup should furnish a plane layer close to every signal layer. Incorporating adjacent power and ground planes can also prove beneficial. Placing a decoupling capacitor (11) near a via can aid completing the return path and diminishing energy loss. The connectors need to provide sufficient number of return path connections. The same signal trace reference should be utilized on both sides of a connector (11). Routing a high-speed signal across a plane gap should be avoided whenever possible.

A plane split can interrupt the return current, as discussed in Part 1, and adversely affect EMI, crosstalk, signal rise/fall times, inductance or impedance. TDR can be applied for examining impedance changes in single-ended and differential traces due to crossing of moats. A set of TDR measurements was conducted employing an Agilent 86100A Infiniium DCA mainframe with an Agilent 54754A differential TDR module.

Two Agilent demo boards were utilized (12). Each included a single-ended microstrip and an edge-coupled differential pair. The single-ended traces had variable width (hence links of various impedance) along their length. FIGURE 4 depicts the demo board traces with SMA connectors at each end.

[FIGURE 4 OMITTED]

One of the test boards had a solid reference ground layer while the second board had a ground plane with a 1-inch wide gap. The yellow region highlights the plane gap's area.

Prior to DUT measurements, a sufficient warm up period was allowed and calibration and normalization were performed (13) to produce accurate TDR data.

FIGURES 5a and 5b reveal that the peak impedance of the single-ended line increased due to crossing a void. Regardless of a moat's width, the impedance increases in the region associated with the signal crossing the void because of a larger return path loop (causing the inductance to increase) and a decrease in the capacitance (6).

[FIGURE 5 OMITTED]

TDR measurement results for the differential pair are presented by FIGURES 6a and 6b. They illustrate that differential impedance has increased due to the traversing of the gap.

[FIGURE 6 OMITTED]

The highlighted region on Figure 6b displays the extent of the plane gap. TDR results indicate that crossing the plane slot has less effect on the differential pair vs. single-ended because each signal in the pair is affected identically (6) due to traversing the plane void.

Additionally, a gap in the return path causes a significant increase in crosstalk for single-ended traces due to high mutual inductance. Hence, whenever traversing a gap is unavoidable, it is preferable to consider a differential pair (14) (as compared to single-ended) that can cause lesser distortion of the signal, although some increase in differential impedance and little common-mode voltage.

The TDR test board had a large gap (1 inch) to simplify measurement of effects. The splits in high-speed PCBs are usually much narrower. A common value for power-plane moat is ~ 10 mils.

The return path for a high-speed signal is not limited to PCB structures but usually extends inside IC packages (15) of the driver and receiver devices. Subsequently, the package bond wires, traces, power/ground planes (16) and solder balls contribute to the signal loop area. The IC pin out may provide useful information regarding package structure. For instance, a signal net encircled by ground pins is probably ground referenced (15) on the package and the same referencing is preferred on a PCB towards optimizing the return path.

A topology was defined using Signrity's Speed 2000 to investigate signal degradation caused by a high-speed signal traversing a plane split (16) inside an IC package. The topology included three microstrip traces as illustrated by FIGURE 7. Two cases were simulated: 1) the reference plane was a solid ground, and 2) the reference plane contained a slot. The void area is highlighted yellow.

[FIGURE 7 OMITTED]

Each trace had a driver consisting of a current source in parallel with a 50-Ohm resistor. The current source outputted a pulse with 100ps rise/fall times, 300 ps duration and 50-mA amplitude. The load end of each trace connected to a 60-Ohm resistor.

The package trace dimensions included 2-inch length, 2.8-mil width and 1.2-mil thickness. The edge-to-edge spacing of adjacent tracks equaled 5.12 mils. The dielectric substrate thickness equaled 3.94 mils with a dielectric constant of 4. Multiple/coupled traces were defined since coupling effects happen frequently in IC packages.

The simulation results for an active net are depicted by Figure 8. A comparison of FIGURE 8a and 8b reveals changes in both the driver (in red) and load (blue) waveforms because of impedance discontinuities created by plane slot. The signal rise time has been slowed/degraded due to traversing of plane gap.

[FIGURE 8 OMITTED]

In conclusion, crossing a reference plane void can cause adverse effects such as rise time degradations, impedance discontinuities, EMI noise and crosstalk. These adverse effects may be diminished by proper use of stitching capacitors (discussed in Part 1). The required number of stitching caps is directly proportional to the number of signals crossing plane gaps. The negative impacts of split reference planes on EMI and signal integrity can be further minimized by applying an effective termination (17) scheme. For an inner layer, sandwiched between a uniform ground layer and a plane with multiple power islands, a logical strategy is to design the stackup with the inner signal layer placed close to the solid ground and far from the split power plane.

Ed. Part 1 appeared in the February issue. The entire column can be viewed online at pcdandm.com/cms/content/view/3269/95

ACKNOWLEDGEMENTS

My gratitude to Mahrokh Esfandiary and Dean Gonzales for helpful discussions. Special thanks to John Dorighi of Agilent Technologies for furnishing the TDR test board with split plane.

REFERENCES

(10.) Bruce Archambeault, "EMC Effects from the Hidden Schematic'; Printed Circuit Design and Manufacture, January 2007, P. 18.

(11.) Scott McMorrow, "Handling Signal Return Current" Printed Circuit Design, September 2002, PR 12-16.

(12.) "User's Guide Agilent 54753A and 54754ATDR Plug-in Modules "Third edition, Agilent Technologies, 2000, PR 7-19 to 7-23. PP. 8-10 to 8-13.

(13.) Abe Riazi, "TDR For Differential Pair Characterization" Printed Circuit Design and Manufacture, September 2005, PP. 16-18.

(14.) Eric Bogatin, "Differential impedance finally made simple" Bogatin Enterprises 2000.

(15.) Kim Flint, "Seeing the Big Picture" July 2005.

(16.) "Trace Over Split Plane" Benchmark Test Report, Sigrity Inc., April 2002.

(17.) J. Alan Roden, Bruce Archambeault, Ruthie D. Lyle, "Effect of Stitching Capacitor Distance For Critical Traces Crossing Split Reference Planes," IEEE International Symposium on Electromagnetic Compatibility, 2003, PP. 703-707.

DR. ABE (ABBAS) RIAZI is a senior staff electronic design scientist with ServerWorks (a Broadcom Company) in Santa Clara, CA. He can be reached at [e-mail].