EZchip Introduces Two New Low-cost Members of its NP-2 Network Processor Family.SAN JOSE, Calif. -- In the section titled "Availability and Pricing", the year is incorrect. It should read: Q4 2004 (sted Q4 2005). The corrected release reads: EZCHIP INTRODUCES TWO NEW LOW-COST MEMBERS OF ITS NP-2 NETWORK PROCESSOR FAMILY A 10-GIGABIT VERSION WITHOUT A TRAFFIC MANAGER AND A 5-GIGABIT VERSION WITH A TRAFFIC MANAGER EZchip Technologies (a subsidiary of LanOptics Ltd., NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on :LNOP), a fabless semiconductor company A fabless semiconductor company specializes in the design and sale of hardware devices implemented on semiconductor chips. It achieves an advantage by outsourcing the fabrication of the devices to a specialized semiconductor manufacturer called a semiconductor foundry or "fab. providing high-speed network processors, is disclosing details of two new low-cost members to its previously-announced NP-2 family of network processors. The NP-2/5 is a duplex 5-Gigabit network processor with two integrated traffic managers to be used in 5-Gigabit applications. The NP-2/10L is a duplex 10-Gigabit network processor aimed at 10-Gigabit applications using optional external traffic managers. Both NP-2 devices integrate a full-duplex network processor, classification engines, ten 1-Gigabit and one 10-Gigabit Ethernet MACs and two SPI (1) (Stateful Packet Inspection) See stateful inspection. (2) (Service Provider Interface) The programming interface for developing Windows drivers under WOSA. 4.2 interfaces with up to 192 channels. The NP-2/5 also features two integrated traffic managers for ingress An entrance. Contrast with "egress," which means exit. See ingress traffic. See also Ingres 2006. and egress See ingress. priority queuing and bandwidth guarantees. Both these models provide the lowest system cost and power for high-density Metro Ethernet and Ethernet over SONET/SDH applications and are offered in addition to the previously announced duplex 10-Gigabit NP-2 with two integrated traffic managers. Sampling for all the announced NP-2 devices is slated for the fourth quarter of 2004, using TSMC TSMC Taiwan Semiconductor Manufacturing Company, Ltd TSMC Taiwan Semiconductor Manufacturing Corporation TSMC Traffic Systems Management Center TSMC Toll Station Management Controller TSMC Transportation Supply Maintenance Command TSMC Technical Services Manager Code 0.13 micron process. The NP-2/5 and NP-2/10L are priced at $445. The NP-2 family is based on the proven architecture of the popular NP-1c, using the same simple programming model, and is software compatible to the NP-1c. All NP-2 models are software and pin compatible to enable customers to build their line cards once and offer them at different configurations and price points using the different NP-2 models. "EZchip already offers the leading 10 Gbps network processors, but not everyone needs 10 Gbps today," noted Linley Gwennap, principal analyst of The Linley Group. "The new NP-2 devices enable EZchip to pursue more price-sensitive OC-48 and multiple-GigE applications, thus increasing the company's total available market significantly." "The additional NP-2 models are provided in response to our large customers' demand to use our technology in more applications within their own product portfolio," said Eli Fruchter, President and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of EZchip. "We will continue to add new members to the NP-2 family to address more applications and increase our total available market including a 20-Gigabit, single-chip, full-duplex device that will further increase the level of integration and reduce system chip count, power and cost." About the NP-2 Network Processor Family The NP-2 is a highly integrated network processor family featuring 5-Gigabit and 10-Gigabit full-duplex processing in a single-chip. The NP-2 integrates several functions that would normally be found in separate chips: 7-Layer packet processing, classification search engines, two traffic managers for ingress and egress traffic management, ten 1-Gigabit and one 10-Gigabit Ethernet MACs and two duplex SPI4.2 interfaces. The NP-2 uses commodity DRAM for all its lookup tables, frame memory and traffic management control to minimize system cost and power dissipation. For maximum flexibility a choice of DRAM technologies are supported: SDRAM (Synchronous DRAM) A type of dynamic RAM (DRAM) memory chip that has been widely used since the late 1990s. SDRAM chips eliminated wait states by dividing the chip into two cell blocks and interleaving data between them. DDR-II, FCRAM-II and RLDRAM-II. Integrated classification search engines eliminate the need for expensive and power-hungry CAMs or even SRAMs. All types of look-up and classification tables are stored in low-cost low-power DRAM and provide large headroom for application scaling. Two traffic managers provide advanced Quality of Service by supporting DiffServ and IntServ services and a wide variety of mechanisms including: per-flow metering, policing and shaping, WRED WRED Weighted Random Early Detection WRED Weighted Random Early Discard WRED Women and Rural Economic Development congestion The condition of a network when there is not enough bandwidth to support the current traffic load. congestion - When the offered load of a data communication path exceeds the capacity. avoidance, as well as priority or WFQ See traffic engineering methods. hierarchical scheduling. For accurate bandwidth control, a separate traffic manager is provided for both the ingress and egress traffic flows enabling traffic shaping and scheduling after processing has been completed, and prior to transmission to the network ports or switch fabric. Each of the traffic managers with its associated memory chips can be bypassed in applications that use external traffic managers. The on-chip MACs provide direct connection to ten 1-Gigabit and one 10-Gigabit Ethernet ports eliminating the need for external MACs. The two SPI4.2 interfaces can bypass the integrated MACs and provide flexibility to connect to switch fabrics and Ethernet or SONET/SDH framers. Up to 192 channels are available supporting virtual concatenation and hitless bandwidth allocation through the Link Capacity Adjustment Scheme Link Capacity Adjustment Scheme or LCAS is a method to dynamically increase or decrease the bandwidth of virtual concatenated containers. The LCAS protocol is specified in ITU-T G.7042. (LCAS LCAS Link Capacity Adjustment Scheme (SDH/SONET Virtual Concatenation) LCAS Lake County Astronomical Society (Illinois) LCAS Licensed Clinical Addictions Specialist ). Availability and Pricing The NP-2/5 and NP-2/10L are scheduled to sample in Q4 2004 and priced at $445 in quantities. About EZchip Technologies EZchip Technologies (a subsidiary of LanOptics Ltd., NASDAQ: LNOP) is a fabless semiconductor company providing high-speed network processors. EZchip's breakthrough TOPcore(R) technology provides both packet processing and classification on a single chip at wire speed. EZchip's single-chip solutions are used for building networking equipment with extensive savings in chip count, power and cost. Highly flexible 7-layer processing enables a wide range of applications to deliver advanced services for the metro, carrier edge and core and enterprise backbone. For more information on EZchip, visit our web site at http://www.ezchip.com. "Safe Harbor Safe Harbor 1. A legal provision to reduce or eliminate liability as long as good faith is demonstrated. 2. A form of shark repellent implemented by a target company acquiring a business that is so poorly regulated that the target itself is less attractive. " statement under the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and of 1995: This release contains forward looking statements that are subject to risks and uncertainties, including, but not limited to, the impact of competitive products, product demand and market acceptance risks, customer order cancellations, reliance on key strategic alliances, fluctuations in operating results, delays in development of highly-complex products and other risks detailed from time to time in LNOP filings with the Securities and Exchange Commission. These risks could cause the Company's actual results for 2004 and beyond to differ materially from those expressed in any forward looking statements made by, or on behalf of LNOP. |
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