DynaChip Announces Production of 200MHz FPGA With TSMC, Achieving Industry-leading Yields and Performance.
SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 15, 1999--
DynaChip's DY6055 targets high-speed computing market with 15 million transistors on a three square centimeter chip and exceptional
DynaChip Corp., a Sunnyvale, Calif.-based supplier of FPGAs for high-speed data communications, telecommunications, computing, emulation, and automatic test, and Taiwan Semiconductor Manufacturing Company (TSMC TSMC Taiwan Semiconductor Manufacturing Company, Ltd
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TSMC Technical Services Manager Code ) (NYSE NYSE
See: New York Stock Exchange :TSM) today jointly announced volume production of the DY6055 FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. .
Built on TSMC's 0.35-micron process technology, the DY6055 achieved a defect density of 0.13 on a three square centimeter chip that supports 15 million transistors and exhibits significantly higher performance than competing devices with similar gate densities.
"With DynaChip's DY6055 FPGA, TSMC has again demonstrated its ability to deliver high sort yields and exceptional performance," said Magnus Ryde, president of TSMC, USA. "TSMC's ability to provide processing services for a wide variety of devices allows us to offer advanced IC technologies that help our customers remain competitive in both product performance and price."
DynaChip's DY6055 FPGA, a member of the company's DY6000 family of high-performance FPGAs, incorporates improvements in internal architecture and I/O versatility. Designed specifically for high performance from the ground up, the DY6000 products are the industry's first FPGAs to support a flexible 66 MHz, 64-bit PCI (1) (Payment Card Industry) See PCI DSS.
(2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). core with sustained bursts with zero wait states. The device significantly out-performs FPGAs with similar gate densities made by competing FPGA suppliers.
"We are very proud of this joint accomplishment with TSMC," said Madhu Vora, Chairman, DynaChip Corporation. "The high sort yield and performance that TSMC delivered helps us to offer system clock rates and chip-to-chip data-transfer rates approaching 200 MHz to meet the increasingly high-speed requirements of the data communications and telecommunications markets. With continuous support from TSMC, we expect to achieve even higher performance with 0.25-micron process technology in 2Q 1999 and gate densities comparable to the leading FPGA vendors. Such outstanding results have given us the confidence to plan a product family using a 0.18-um process from TSMC. We expect the 0.18-micron family to be available in Q1 2000."
The DY6000 is the first FPGA family to incorporate a two-clock, dual-port RAM in every logic block; PLLs (phase-locked loops) that operate up to 205 MHz with programmable clock latency from -4.0 to +2.0 ns in increments of 150 ps; and flexible interface levels, including differential PECL PECL PEAR (PHP Extension and Application Repository) Extended Code Language
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PECL Positive Emitter Coupled Logic
PECL Pseudo-Emitter Coupled Logic
PECL Positive-Referenced Emitter Coupled Logic , LVDS (Low Voltage Differential Signaling) A transmission method for sending digital information. LVDS sends data over data high and data low lines rather than data and ground. , GTL, GTLP GTLP Gunning Transceiver Logic Plus (family of logic integrated circuits) , and LV-TTL.
Implemented in 0.35-micron, the DY6055 contains 15 million transistors and 55,000 usable gates. Its distributed RAM architecture provides total flexibility on FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods.
FIFO - first-in first-out word widths by enabling the placement of the FIFO next to the pins and/or the logic it talks to, thus eliminating routing congestion The condition of a network when there is not enough bandwidth to support the current traffic load.
congestion - When the offered load of a data communication path exceeds the capacity. and allowing very high-speed operation. The DY6055 can implement up to 34 FIFOs with 32-bit word widths, or 14 FIFOs with 73-bit word widths running at speeds of 125 MHz. The DY6055 is available in either a 240-pin QFP (quad flat pack) for $174 per1000 or a 432-pin BGA (ball grid array “BGA” redirects here. For other uses, see BGA (disambiguation).
A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. ) for $229 per1000.
DynaChip Corporation, founded in 1993, is the inventor of the Active Repeater(TM), a new patented active programmable interconnect element. The company offers three families of Fast Field Programmable Gate Arrays that bring the benefit of programmable logic to high-speed applications in communications and test. The company is located at 1255 Oakmead Parkway, Sunnyvale, CA 94086; telephone: (408) 481-3100; Fax: (408) 481-3136; Web site: http://www.dyna.com.
TSMC (ADS traded NYSE:TSM, also traded on TSE See Tokyo Stock Exchange.
1. See Tokyo Stock Exchange (TSE).
2. See Toronto Stock Exchange (TSE). ) is the world's largest dedicated integrated circuit (IC) foundry and offers a comprehensive set of IC fabrication processes, including processes to manufacture CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. logic, mixed-mode, volatile and non-volatile memory and BiCMOS chips. Currently, TSMC operates two six-inch wafer fabs (Fab 1 and 2) and three eight-inch wafer fabs (Fab 3, 4 and 5), all located in Hsin-Chu, Taiwan. In mid-1998, TSMC announced that production wafers were being delivered from its first U.S. foundry, WaferTech, a joint venture with Altera, Analog Devices and Integrated Silicon Solutions, Inc. The company has broken ground in the new Tainan Park, which will house Fabs 6 and 7 and recently announced its participation in a $1.2 billion joint venture fab with Philips Semiconductor which is scheduled to open in Singapore in 2000.
Note to Editors: TSMC's corporate headquarters are in Taiwan. More information about TSMC is available through the World Wide Web at www.tsmc.com.tw.