Don't snub via stub induced signal distortions.

Regarding Eric Bogatin's "Only Two Knobs to Tweak Above 3 GBps" article in the July 2006 issue of Printed Circuit Design & Manufacture, I would like to add a third important factor--via stub induced signal distortions. As a general rule, migration of high performance interconnects to higher speeds also require a reduction in bit error rate (BER) of approximately 3 orders of magnitude for every doubling in data rate. For example, if an existing BER requirement at 3.125 Gb/s is 10^(-12), then the BER performance at 6.25 Gb/s needs to be around 10^(-15) and 10^(-18) at 12.5 Gb/s.

In other words, BER is a more important design driver than data rate for tomorrow's high performance interconnects. BER is highly dependent on signal distortion--not signal level. (Given a choice, every semiconductor compensation design engineer that I have talked to would rather have a signal at the receiving end that is attenuated but not distorted--instead of a signal that is distorted but not attenuated.) Signal distortion in turn is a function of the "slope" of the attenuation curve, not the absolute magnitude of the attenuation at a given frequency as noted in Bogatin's article. It is a commonly known fact within the high performance signal integrity community that via-stub induced reflection and self-resonance losses introduce steep slopes in the overall interconnect attenuation curve that can easily be 10 to 100 times steeper (worse) than those introduced by the conductor skin depth and dielectric losses outlined in Bogatin's article.

Interconnects having multiple via stubs--a common occurrence--also introduce interconnect memory losses that further aggravate inter-symbol interference (ISI), a particularly problematic form of interconnect distortion. Switching to a higher performance dielectric material will not magically compensate for (e.g. remove) the detrimental effects of via stubs on signal quality and BER. Furthermore, if the via stubs are not removed from the interconnect, then a significant portion of the semiconductor pre/de-emphasis and receiver equalization horsepower will have to be diverted to compensating for the via stub effects instead of being allocated to trace/dielectric losses.

A variety of PCB design and manufacturing techniques exist to effectively reduce the effects of via stubs including backdrilling, controlled depth drilling (mechanical and laser) and the use of microvias. For example, backdrilling out via stubs during the PCB manufacturing process will often double or triple the useable bandwidth of an interconnect--with significant reduction of BER--for a nominal incremental cost that is usually much less than migrating to more expensive dielectric materials or more sophisticated semiconductor compensation schemes. Further enhancement of the portion of the via that remains after the backdrilling operation, using for example, Sanmina-SCI's patent-pending OptiViaT optimization algorithm can also extend the useable bandwidth.

Sincerely,

Franz Gisin

Director, Backplane Design Technology

Signal Integrity Design

Sanmina-SCI

Eric Bogatin's reply:

Dear Mr. Gisin,

The point of my column wasn't that the only two things you have to worry about is the dissipation factor of the laminate or the use of TX or RX equalization. It was that attenuation from the laminate happens. It is the inherent nature of dielectric loss to have an attenuation that increases linearly with frequency. This frequency dependence is what causes the rise time degradation, so an attenuation value from dielectric loss is a reasonable first order measure of the ISI, collapse of the eye and deterministic jitter.

Attenuation from the laminate is a first order term, and is the dominant effect influencing the BER in long high-speed serial links. The only two ways of dealing with it are to use a lower loss laminate or to use a SERDES technology, which incorporates some sort of TX and/or RX equalization feature. Both of these cost more money. This is where the cost trade-offs must happen. As bit rate increases for long lines, such as backplanes, should the investment be made in lower loss laminates or in higher cost silicon SERDES technologies? These are the two knobs available to adjust.

You have an excellent point that even with the world's lowest loss laminate, if you haven't fixed the via stub problem, which your backplane technology does a superb job of, the BER can be killed by just a few hundred mils of via stub. Fixing the via stub problem just allows you back in the game to then worry about the rise time degradation from the frequency dependent dielectric loss.

In fact, as you point out, the issue of the distortion from the via stubs is another critical factor influencing the BER in high-speed serial links. Based on your comments, I think I will use this as the topic of one of my next columns.

Eric Bogatin

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