Does your design need HDI? HDI is more expensive process, but overall product cost can be lower thanks to fewer layers and smaller boards.

The drive to produce more handheld applications is well documented, but Mother Nature plays a big role in determining the other drivers. As chip signal rise times decrease due to smaller gate geometries, the resulting signals are more susceptible to interconnect parasitics (1). Signal integrity improves with miniaturization. All these smaller size factors are drivers for HDI with microvias.

Semiconductor complexity increases (in the number of total gates) require more pins for integrated circuits as well as finer pin pitch. Over 2,000 pins on a 1.0 mm-pitch BGA is not unusual, nor are 296 pins on a 0.65 mm-pitch device. The faster rise times, as well as the need for SI, require an increasing number of power and ground pins. Consequently, this drives the need for layers in multilayer boards. Again, this drives the need for HDI with microvias. Microvias are the principal feature of HDI, along with thinner dielectrics and smaller traces and spaces.

The first question to ask is, Do I need HDI? This is a very important question, as HDI is a more expensive process than conventional circuit board manufacturing. The major HDI drivers are:

* Lower costs, thanks to fewer layers and smaller boards.

* Reduction in layer count for thickness control and reliability.

* Miniaturization for portable products.

* Improved electrical performance and SI.

* Reduced EMI and RFI.

* Higher component density and component I/Os.

* Integration of fine-pitch devices.

The Dish on High Density

Cost. Making boards smaller provides savings, as affords wiring components with fewer layers. The reduction in total layers will usually pay for the extra steps required for microvia fabrication. If the materials happen to be more expensive than FR-4, such as low-loss laminates, then the savings can be quite significant. The fact that the board can be made smaller provides more significant savings in the images manufactured on a production panel. It usually doesn't make economic sense to use HDI for low layer-count boards. Cost reduction through HDI usually begins with PCBs of at least 10 layers (on FR-4), and savings are almost always found when dealing with boards of 18 layers or more.

Density. As discrete components continue to get smaller with the increasing use of 0402s and 0201s, and BGAs make up more of the IC packages, the total number of connections on both sides of a board increases. When the average connections per [in.sup.2] begin to exceed 100 pins (connections) (or 15.5 pins per [cm.sup.2]), there is less room to wire up these devices. The space occupied by the SMT land pattern, the through-hole via and the traces that connect them begin to exceed what you can put in a single [in.sup.2]. This is the approach to the "through-hole barrier" in FIGURE 1a. Beyond around 120 connection/[in.sup.2], design rules have to be severely cut and additional layers added to complete the interconnect (FIGURE lb). The layer count begins to rise exponentially. Remember that 1.0 mm-pitch devices can benefit from HDI, but 0.8 mm-pitch devices permit HDI to really provide advantages. The blind vias save room on innerlayers and have reduced via lands, and make via-in-pads possible. Typical of these devices is the 240 pin, 0.65 mm-pitch DSP.

[FIGURE 1 OMITTED]

High I/O area arrays. The other new components becoming more widespread are those with very high pin counts: 600 to 2,500 pins, even at 1.27 mm and 1.0 mm pitches. Although some of these are telecom digital switches, the vast majority are FPGAs. Current products from Infineon, Xilinx and Altera include packages with 204, 348, 396, 564, 692, 804, 852, 996, 1,164 and 1,200 pins.

Design time. Layout and routing time is greatly speeded through the use of blind vias, because the via does not interfere with placement and breakout of components on the opposite side of the board. The addition of buried vias that connect to blind vias permit most autorouters to go to almost 100% completion. This can trim weeks from the layout of critically dense boards.

High frequencies. The very fast rise times of newer ICs and the increase in high-frequency circuits make these devices more sensitive to noise and signal interference. HDI interconnects are much smaller and the blind vias have 1/10 the inductance and capacitance of through-hole vias. A microvia will not have a significant reflection of fast moving signals until nearly 25 GHz, while through-holes will reflect about 10% of any signal that is 2 GHz or faster.

Buried passives. As buried passives become more popular and go into production, the primary interconnect to these components will be the microvia. The smaller via and its more accurate placement with optically aligned laser drills permit placement under or near critical components, and with very little inductance.

Implementing HDI

Once you decide that HDI is going to play a role in your next board design, the first thing to do is become familiar with the basics, especially IPC HDI standards and guidelines:

* IPC-2226, "Sectional Design Standard for High Density Interconnect (HDI) Printed Boards."

* IPC-4104, "Specification for High Density Interconnect (HDI) and Microvia Materials."

* IPC-6016, "Quality and Performance Specification for High Density Interconnect Layers or Boards."

* IPC/JPCA-2315, "Design Guide for High Density Interconnects (HDI) and Microvia."

* IPC-9151, "Printed Board Capability, Quality and Relative Reliability (PCQ[R.sup.2]) Benchmark Test Standard and Database."

IPC-2226 advises to select the minimum and simplest technology/architectures. These are the Type I through Type III HDI structures. The density tradeoff tutorial in IPC/JPCA-2315 and IPC-2226 is very helpful in understanding the density tradeoffs that will be discussed here.

The selection of signal layer stackup and design rules determines the maximum wiring capability (Wc) for a design. The schematic and total component parts list, along with their connections, can be used to estimate the total wiring lengths required to connect this design. This is the wiring demand (Wd). The actual wiring capacity is the maximum wiring capacity multiplied by the design's layout efficiency (LE). Per Holden (2), the actual wiring capacity must always be larger than the wiring demand

Wd [less than or equal to] LE * Wc.

Layout efficiency (LE) is the ability to deliver the design rules to the final product. The higher the layout efficiency, the smaller or fewer signal layers will be required. LE of 100% is the maximum wiring capacity (Wc). Since no PCB actually looks like this, the actual LE is normally between 8% and about 25%. The layout efficiency with blind and buried vias can be as high as 60%. This is one reason that HDI designs require fewer layers.

Via structures are the central features in HDI stack-ups. Three microvia structures are used to connect components adjacent microvias (a dogbone); inset microvias (near-via-in-pad) and via-in-pad (FIGURE 2). Via-in-pad occupies the least amount of space, is easiest to design and boasts the fewest parasitics. But it is also the one structure likely to give the assembler trouble with trapped air, especially under BGA balls. This has led to the inset microvia or "near-via-in-pad," in which the microvia is next to the SMT land and covered with soldermask. The space occupied by the inset via is small enough to permit flooded ground planes into the BGA array, where an adjacent via (dogbone) takes up too much space. As seen in FIGURE 3a and FIGURE 3b, even with 0.8 mm-pitch devices, the "inset-via" permits copper into the array.

[FIGURES 2-3 OMITTED]

A new trend is plugging through-holes with a conductive paste and then plating a surface cap on the plugged via. When this is applied to via-in-pads, increased density is possible. FIGURE 4a and FIGURE 4b show the primary and secondary side of a very dense 10qayer board. This board averaged 165 connections (pins)/[in.sup.2] on both sides. The fine-pitch BGA in FIGURE 4d is a 1.0 mm, 484 pin ASIC. The wiring was facilitated by not having to use via dogbones on this part, as the drilled vias were placed in the 0.020" SMT lands. The discrete components were also very dense. FIGURE 4c shows the decoupling capacitors on the opposite side of the board from the two primary ASICs. The smaller BGA is a full array 0.8 ram, 320 pin BGA with through-hole, filled vias in the SMT pads of the discretes.

[FIGURE 4 OMITTED]

One very useful HDI design technique is to use blind vias to open more routing space on the innerlayer, especially channels to reach inner pins on area array parts (FIGURE 5). By using blind vias, the routing space effectively doubles on the innerlayers and many more traces can be used to connect pins on the inner rows of a BGA. The placement of these blind vias to form a channel on the innerlayer is called a channel routing via structure, a process patented by Nortel Networks in 2002. (3) With this technique, only one-half to one-third the number of signal layers are required to connect a complex high I/O BGA. PCD&M

REFERENCES

(1.) Happy Holden, "HDI's Beneficial Influence On High-Frequency Signal Integrity;' Mentor Graphics technical paper: www.mentor.com/pcb/ tech_papers.

(2.) Happy Holden and R. Charbonneau, "Predicting HDI Design Density" The Board Authority, vol. 2, no.1, April 2000, pp. 28-31.

(3.) Nortel Networks patents 6,388,890 and 6,545,876,

HAPPY HOLDEN is manager of advanced technologies for Westwood Associates (westwoodpcb.com). He has over 30 years of experience in PCB engineering, R&D and manufacturing, including 27 years at Hewlett-Packard. Holden can be reached at [e-mail].