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Distinguished IC Design and CAE Experts Launch HDAC, Inc.; New EDA Company to Provide the Next Generation Tools for Design & Verification of Complex ICs and IP Blocks.


ALAMEDA, Calif.--(BUSINESS WIRE)--March 29, 1999--Two distinguished researchers in integrated circuit (IC) and computer-aided engineering (CAE (1) (Computer-Aided Engineering) Software that analyzes designs which have been created in the computer or that have been created elsewhere and entered into the computer. ) software design announced the formal launch of HDAC HDAC Histone Deacetylase (biochemistry)
HDAC Heavy Duty Air Cylinder
, Inc., a new electronic design automation (EDA) company focusing on design and verification of complex ICs and digital intellectual property (IP).

HDAC was organized and incorporated in March of 1997 by Dr. Ramin Hojati, President. Dr. Mehran Massoumi, HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards.  Architect, joined the company in November of 1998. The EDA startup has received funding from a group of private investors.

"Verification is still the number one problem for circuit designers," said Ramin Hojati, President and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board.  of HDAC.

"Design complexity continues to grow with the advent of smaller chip geometries and the need for systems on a chip, but today's verification tools are falling behind with respect to delivering fast functional verification that guarantees correct designs. Furthermore, current simulation verification products force designers to implement a methodology that requires numerous interactions between tools that slow the design process.

"Just running a test bench on today's large ASICs still takes too long and is too painful a process. HDAC overcomes the verification bottleneck with unique static verification technology that guarantees correctness with lightning fast speed, in a single easy-to-use environment. HDAC accelerates the verification process and fits with a synthesis-driven and IP reuse design methodology. We want to put static functional verification on every designer's desktop."

HDAC has developed an integrated software design tool that delivers static functional verification for designers of ASICs, IP cores and programmable parts. The company's future products will address the needs of chip designer including integration and system-level verification, and both pre- and post-synthesis analysis.

Founders Deliver Practical Design Solutions

HDAC's principals possess extensive background in both software tool development and the actual design of complex ICs, which serve as its foundation for strategic direction. Dr. Hojati has been a design verification consultant to Cisco, Compaq, IBM, SGI, and SUN Microsystems. Dr. Massoumi has worked for many years in the development of practical synthesis tools for FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market.  designers.

Hojati obtained his M.S. and Ph.D. in computer science in 1992 and 1996, respectively, from the University of California, Berkeley The University of California, Berkeley is a public research university located in Berkeley, California, United States. Commonly referred to as UC Berkeley, Berkeley and Cal . At UC Berkeley, he was the main driving force behind Berkeley's first generation verification system, HSIS HSIS Highway Safety Information System
HSIS Health Supplements Information Service
HSIS Human Systems Integration Symposium
HSIS High Speed Interface/SNA
HSIS High-Speed Image Server
. Before that, he was the author of the first BDD-based engine for Lucent Technologies FormalCheck. He obtained his B.S. from Massachusetts Institute of Technology Massachusetts Institute of Technology, at Cambridge; coeducational; chartered 1861, opened 1865 in Boston, moved 1916. It has long been recognized as an outstanding technological institute and its Sloan School of Management has notable programs in business,  in 1988 in math and computer science. From 1988 to 1990, he worked on layout and logic synthesis tools at Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services.

http://cadence.com/.

See also Verilog.
.

Massoumi obtained his M.S. and Ph.D. in Computer Engineering from the University of Arizona (body, education) University of Arizona - The University was founded in 1885 as a Land Grant institution with a three-fold mission of teaching, research and public service. , respectively, in 1987 and 1994. From 1990 to 1997, he worked on FPGA logic synthesis tools at Viewlogic Systems. Subsequently, he joined the FPGA synthesis team at Synopsys until November 1998. Also, during his tenure at Viewlogic, he served as a faculty member in the Computer Science and Engineering Department at Northern Arizona University Northern Arizona University (NAU) is a public university in Flagstaff, Arizona in the United States.

As of Fall 2007, the university has 21,352 students, 13,989 of these are situated in the main Flagstaff campus<ref name="Enrollment" />.
.

"Our experience with verification and synthesis of actual designs, gave us the direction to develop a breakthrough verification tool. Designers are struggling with the current set of tools, and we are committed to creating tools that are practical for design and not just products of academia," said Hojati.

Support from EDA Industry Veterans

In addition to the strong background of its founders, HDAC has the support of the highly regarded EDA industry veterans on its board of directors and technical advisory board. Each has made significant contributions in areas of logic synthesis, simulation, and verification. Company directors include:

-- Manuel Correia: Executive VP & COO, CoWare

-- Dr. Warren Wong: Senior Director of R&D, Synopsys

-- Dr. James Wilcox: Professor, Haas School of Business, U.C.

Berkeley

Dr. Robert Brayton, Professor & Director of the SRC (SouRCe) Contrast with DST, which is an abbreviation of "destination."  Center of Excellence for Design Sciences, U.C. Berkeley, serves on HDAC's technical advisory board.

Product Introduction

HDAC will make its first public showing as an exhibitor at 1999 International HDL Conference & Exhibition, in Santa Clara, California Santa Clara, California (IPA: /ˌsæntəˈklærə/) , founded in 1777 and incorporated in 1852, is a city in Santa Clara County, in the U.S. state of California. , the week of April 5th. Its first products will ship in June and will be on demonstration in booth 105. HDAC will also be showing at the Design Automation Conference in New Orleans in June.

About HDAC

HDAC, Inc. is a pioneer in the new market for static functional verification. The company delivers interactive analysis software for RTL designers, architects, and validation engineers that improves design quality, shortens design cycles, and eliminates unnecessary simulation. HDAC's products are easily incorporated into synthesis and IP reuse design flows.

HDAC can be reached at (510) 864-7587, on the web at www.hdac.com or by email at info@hdac.com
COPYRIGHT 1999 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 1999, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Geographic Code:4EXPO
Date:Mar 29, 1999
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