Differential signals routing requirements: for noise immunity, complementary transmitted signals need to be well balanced and trace impedances symmetrical.

DIFFERENTIAL SIGINALING INVOLVES two complementary signals of equal amplitude but opposite phase (1). One signal is referred to as positive (non-inverted) and the other called negative (inverted) (2). Differential transmission is gaining in application and importance (3) due to increasing data speeds. For instance, numerous high-speed clock signals in motherboards of PCs and servers are designed as differential pairs. And LVDS (low voltage differential signaling) technology (4) is applied in many devices such as printers, switches, routers and audio/video digital signal processing.

Compared to single-ended transmission, differential signaling demands more complex (5) drivers and receivers plus twice the number of interconnect leads. On the other hand, differential offers several attractive advantages (6) over single-ended:

* More precise timing.

* Higher operational speed.

* Greater immunity to EMI and crosstalk coupled noise.

When routing differential traces, it is generally desirable that the two traces possess the same impedance, bc of equal length, and that the edge-to-edge separation between the pair is constant.

Using an example, let us explore several important concepts of differential routing. FIGURE 1 depicts a differential net routed on a motherboard between pins of an ASIC and a connector (for plugging in a memory daughterboard). The green net is the non-inverting and the red one represents the inverting signal. Each net includes two vias and serpentine section.

[FIGURE 1 OMITTED]

FIGURE 2 magnifies the region near the ASIC side of Figure 1. FIGURE 3 focuses on the connector side of Figure 1. Figures 1 through 3 reveal several useful rules of differential routing including:

[FIGURES 2&3 OMITTED]

* The component pins for connection of inverting and non inverting pins are usually adjacent/close to each other.

* The corresponding positive and negative trace segments are frequently routed on the same layer and adjacent to each other with uniform spacing.

* Wherever the traces change layers, the air gap separation of the two associated via pads is minimized (not to exceed trace spacing, if feasible).

* Serpentine sections of the two traces are produced in the same relative regions so that the positive and negative signals can achieve matched delay to any point along the net.

Minimizing skew between the two differential traces (7) and achieving matched lengths are key considerations.

However, in addition to the traces on the PCB, the IC package itself can have traces extending from each pad to the pins of the chip. The length difference between such traces inside the package can be significant in some cases. Where, for each net via 1 and via 2 refer to vias closer to connector and ASIC pros respectively. Subsequently, for gaining optimum timing margins for a high-speed differential net, it is not essential to make the trace lengths equivalent on the PCB; what's more important (whenever length data are available for the package) is to ensure that the sum of PCB trace lengths and package traces are equal (within a specified tolerance) for the pair.

As a numerical example, let us consider the case when the differential lines of Figure 1 assume the following segment lengths:

For non-inverting output signal:

Segment length from connector pin to via 1 = 3022.93 mils

Segment length from via 1 to via 2 = 747.97 mils

Segment length from via 2 to the driver ASIC pin = 27.8 mils

Total net length (for positive signal trace) = 3,798.73 mils

For inverting output signal:

Segment length from connector pin to via 1 = 3025.5 mils

Segment length from via 1 to via 2 = 817.87 mils

Segment length from via 2 to the driver ASIC pin = 27.8 mils

Total net length (for negative signal trace) = 3,871.20 mils

Subsequently, for the PCB routed traces there is a difference of 72.47 mils for the positive and negative lines.

Some of this length difference must be compensated for by the difference in package lengths so that the sum of the traces on PCB and package is less than a specified tolerance (examples: 0.025", 0.010", etc.). Therefore, for this example the package trace length associated with the shorter PCB trace must exceed the package trace associated with the longer PCB trace by approximately 0.062" to 0.082" (assuming the allowed mismatch tolerance is 0.010").

Ed.: Part 2 will he published in the March issue. The entire column can be viewed online at pcdandm.com/pcdmag/mag/0402/0402strategies.pdf.

ACKNOWLEDGMENTS

I would like to express my appreciation to Jeremy Plunkett, Peter Arnold, Dean Gonzales, Danwei Xue, and Abhijit Mahajan for helpful discussions.

REFERENCES

(1.) Howard Johnson and Martin Graham, High-Speed Signal Propagation: Advanced Black Magic, Prentice Hall, 2003, pp. 370-374.

(2.) Dennis Nagle, "Routing Differential Pairs;' Printed Circuit Design & Manufacture, August 2003, pp. 28-30.

(3.) Steve Kaufer and Kellee Crisafulli, "Terminating Differential Signals on PCBs," Printed Circuit Design, March 1999, pp. 25-28.

(4.) Jimmy Ma, "A Closer Look at LVDS Technology," PERICOM application note 41.

(5.) Brian Young, Digital Signal Integrity: Modeling and Simulation with Interconnect and Packages, Prentice Hall, 2000, pp. 391-393.

(6.) Doug Brooks, "Differential Signals" Printed Circuit Design, May 2001, pp. 36-38.

(7.) Bernard Voss, "Routing High Bit Rate Connectors;' Printed Circuit Design & Manufacture, June 2003, p. 30.

ABE (ABBAS) RIAZI is a senior signal integrity engineer with ServerWorks (serverworks.com). He has a Ph.D. in electrical engineering from the University of Utah. He can be reached at [e-mail].