Die attachment technology: a primer on common packages and mounting methods.

In most cases, an IC chip (die) is packaged into a plastic or ceramic enclosure, such as a quad flatpack, small outline package, or one of the newer BGA or quad flatpack no-lead (QFN) packages (Figure 1). These packages are then soldered onto a circuit board. Chip-on-board (COB) (Figure 2) and flip chip on board (FCOB) (Figure 3) are two other ways to attach a die. There are basic similarities in the manufacturing operations for the die attach step in Figures 1 and 2. The die is face-up in both the standard package and the COB direct attachment to the PWB. In contrast, the die in Figure 3 must be flipped so that the face of the die, with its I/O connections, is turned toward the board.

[FIGURE 1 OMITTED]

[FIGURE 2 OMITTED]

[FIGURE 3 OMITTED]

The equipment for the standard package and COB methods of die attach are quite similar, having the capabilities to dispense or print the die attach adhesive and to place the face-up die onto the lead frame or board. However, for flip chip, the equipment must also flip the chip to a face down position, to present the electrical interconnection pads (bumps) to the substrate, with both upward- and downward-looking cameras to align I/O pads and bumps on the die (upward camera) to the conductor pads on the board (downward camera).

Most typical surface mount or die attach machines, however, are equipped only with a downward-looking camera that will align the edges of surface mount components and/or bare integrated circuit die with fiducials or other features of the lead frame or board. For flip chip die placement, this is usually augmented with an upward-looking camera to permit facedown alignment of the flip-chip pads with pads on the board. It should be noted that packages are sometimes made using flip chip for the interconnection of the die, but those packages are usually BGAs or CSPs, in which the "lead frame" is actually a PWB. The purpose of this type of package, with flip chip as the die-attach method, is to minimize electrical capacitance and inductance (parasitics) associated with wire bonds. This method is often used for microprocessors or ASICs with high I/O counts that have the need for excellent signal integrity at high signal speed.

Equipment for attaching die for standard lead-frame-based packages or COB face-up applications uses either solder or adhesive die attachment materials and methods. Placement accuracy has improved; many manufacturers claim five to 10[mu]m accuracy, with +/-1 [mu]m available at a premium. These die placers, combined with recent advances in wire bonding equipment permitting extremely accurate wire length, loop height and loop shape control, permit COB with wire bonding to compete with flip chip in RF applications where the accuracy of the parasitic reactances at each I/O pad of the die is a factor in the overall design. In applications such as this, the extremely precise die position relative to other die in the assembly defines an accurate bond wire length (and therefore resistance) and capacitance and inductance (wire loop control) that can become a predictable and reliable part of the RF design.

Improved die placement accuracy has also benefited facedown flip-chip die attachment. Some flip-chip systems do not enable self-alignment, a phenomenon of the surface tension of liquid solder (molten solder bumps) pulling the die into alignment with the substrate pads. Those applications (using non-melting metal bumps) benefit because the original placement of the flip chip die is now sufficiently precise so self-alignment is not required.

The American Competitiveness Institute (aciusa.org) is a scientific research corporation dedicated to the advancement of electronics manufacturing processes and materials for the Department of Defense and industry. This column appears monthly.