Design Integrator Environment Connects VLSI ASIC Cell Libraries to Popular EDA Tools; Complete Design Flow With Sign-Off Simulation Opens Access to Cadence, COMPASS, Mentor Graphics, Synopsys Tools.

SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 5, 1995--VLSI Technology, Inc.'s (NASDAQ: VLSI) new Design Integrator application-specific integrated circuit (ASIC) design environment migrates design sign-off to end-users by connecting the company's ASIC design libraries to leading third party electronic design automation (EDA) tools.

The environment offers the ASIC industry's first language-based system, permitting data exchange between third party EDA tools and cell-based ASIC design libraries. This creates the ASIC industry's only user-sign-off quality design flow that does not require re-simulation by VLSI Technology centers or manufacturing facilities. In addition, the Design Integrator environment empowers users to utilize industry-leading EDA tools from Cadence, COMPASS, Mentor Graphics and Synopsys.

Bob Payne, VLSI vice president and chief technology officer described the Design Integrator as a strategic move for the company. "The million-gate ASIC era has arrived, and poses a fundamental time-to-market challenge for our customers. The Design Integrator environment is a strategic capability unique to VLSI as it empowers ASIC customers to quickly and efficiently create high-density, high-functionality end-products using the industry's most successful EDA tools."

Product Architecture, Methodology and Features

The Design Integrator environment's language-based architecture seamlessly connects design tools to VLSI cell-based and gate array libraries, which can then be manufactured into finished products with the company's industry leading 0.6-, 0.5- and 0.35-micron fabrication capabilities.

In contrast to net list-based translators that are typically proprietary to various ASIC manufacturers, the Design Integrator tools let users design chips using a hardware description language without any need to translate the design to internal tools and formats prior to manufacturing. This slashes time-to-market and engineering costs for new ASIC designs and increases the probability of first-pass success as new products emerge from the foundry.

The Design Integrator environment consists of four major elements: end-user-selected ASIC EDA tools supplied by third-party software vendors, a multiwindow/multitool graphical user interface, a language-based interface layer connecting tools with the environment's fourth element -- data libraries describing VLSI cell-based and gate array elements.

The Design Integrator environment guides the end-user through a proven methodology from simulation through synthesis, timing analysis, physical design and test pattern generation. The flexible language-based architecture of the environment allows end-users to design end-products using Cadence's Verilog XL and Leapfrog tools, COMPASS' QSIM simulator, Mentor Graphics' QuickSim II and QuickVHDL tools, and Synopsys' VSS simulator.

The Design Integrator methodology incorporates a rich portfolio of VLSI cell-based and gate array libraries, as well as VLSI's cores, such as ARM RISC microprocessor and Pine digital signal processing (DSP) building block, for networking, wireless, computing and consumer products.

Tool Vendor Endorsements

The Design Integrator environment has attracted widespread support from third party EDA tool vendors, who view the methodology as an important means to link their design tools to one of the world's leading ASIC manufacturers. Comments from EDA company representatives include:

As a pioneer in working with silicon vendors to provide sign-off simulation accuracy for ASIC designers, Cadence is pleased to see VLSI providing an even more efficient flow and offering both Verilog XL and Leapfrog VHDL sign-off status to our mutual customers.

Jim Douglas Vice President Marketing Cadence Design Systems, Inc.

We are excited to participate in the Design Integrator series. Many designers want to bring COMPASS' floorplanning, place-and-route, test automation, synthesis and other tools into their existing EDA environment. Design Integrator will help make this integration easier.

Jeff Lewis Vice President Marketing COMPASS Design Automation

VLSI's Design Integrator series provides our mutual customers a thoroughly verified solution for ASIC development using Mentor Graphics' top-down design flow including synthesis, simulation, and design-for-test tools. This second generation ASIC design capability is a key result of the VLSI Technology/Mentor Graphics technical partnership.

Fuad Musa Vice President and General Manager ASIC/Programmable Logic & Test Division Mentor Graphics Corp.

VLSI's language-based Design Integrator series represents a proactive step to better integrate Synopsys' high-level design tool strategy including synthesis, test synthesis and VHDL simulation with VLSI's deep sub-micron libraries. VLSI's new Design Integrator environment positions them to partner with us on the next paradigm shift to source-level design and debug at the RTL and behavioral levels.

Jan Anderson Director, Semiconductor Vendor Program Synopsys, Inc.

Market Analyst Comment

Leading EDA market analysts describe the environment as a significant advance for ASIC design technology and ease-of-use:

The Design Integrator environment addresses some of the biggest problems facing ASIC designers. It loosens proprietary links binding design tools to silicon manufacturers, eliminates some "fifth wheel" design flow steps and provides a powerful solution for deep sub-micron timing analysis.

Jerry Worschel Vice President In-Stat Phoenix, AZ

The Design Integrator series is the most complete solution I've seen for ASIC design. It ties together a lot of loose ends that have held back the full potential of highly-integrated ASIC technology.

Gary Smith, Principal EDA Analyst Dataquest, Inc. San Jose, CA

End-User Involvement

The Design Integrator environment results from close cooperation between VLSI, third party tool vendors and leading ASIC customers. The Design Integrator Customer Advisory Board includes demanding, time-to-market ASIC consumers drawn from the communications, computer, multimedia/entertainment and embedded systems industries.

Roll-Out Program

The Design Integrator Series will be introduced in three phases. Design Integrator Verilog with support for Cadence, Quad, Synopsys and COMPASS tools begins production shipments in the third quarter of 1995. Design Integrator Mentor with support for Mentor Graphics, Synopsys and COMPASS tools will ship production in the fourth quarter of 1995 and will be followed by Design Integrator VHDL with support for Cadence, Mentor Graphics, Synopsys and COMPASS tools in the first quarter of 1996. VLSI quotes pricing for a base Design Integrator environment, exclusive of third party tools, at USD $15,000.

VLSI Technology, Inc. (NASDAQ: VLSI) designs and manufactures application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs) based on its library of FSB functional system blocks. Targeting its offerings towards the communications, computing, and consumer entertainment marketplaces, the company offers its customers advanced system-level integration capabilities. The company headquarters is based in San Jose, California, with 1994 revenues of $587 million, and has approximately 2,700 employees worldwide. -0-

Note to Editors: Design Integrator, FSB and ARM are trademarks of VLSI Technology, Inc. All other trademarks are property of their respective companies.

CONTACT: VLSI Technology, Inc.

Martin Chorich, 408/922-5155