Denali Deploys Verific SystemVerilog Software for Internal Development.ALAMEDA, Calif. -- Verific Design Automation today announced that Denali Software Denali Software, Inc. is an American software company, based in Palo Alto, California. The company produces electronic design automation (EDA) software and intellectual property (IP) design cores for memory and other standard interfaces. has deployed Verific's hardware description level (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) component software for its internal development. Denali licensed Verific's SystemVerilog parser A routine that analyzes a continuous flow of text-based input and breaks it into its constituent parts. See parse. (language) parser - An algorithm or program to determine the syntactic structure of a sentence or string of symbols in some language. , analyzer and static elaborator to be utilized within Denali's internal design tool flow. The SystemVerilog software, delivered to Denali as source code, is written in platform-independent C++ that compiles on Solaris, HP-UX HP's version of Unix that runs on its 9000 family. It is based on SVID and incorporates features from BSD Unix along with several HP innovations. (operating system) HP-UX - The version of Unix running on Hewlett-Packard workstations. , Linux and Windows platforms for both 32- and 64-bit compilers. "We are happy working with Verific, as utilizing SystemVerilog represents a cornerstone of our configurable IP strategy," says Brian Gardner Brian Gardner is an American record producer and sound engineer. He has worked on over 750 recordings since the mid-1970s, including classic rock, funk, disco, alternative rock, R&B, hip hop, pop punk, and dance pop. , vice president of IP products at Denali. "Incorporating their tool into our flows saves us valuable time and resources. We find their customer support and service to be exceptional." "Working with Denali has been a great experience, because it's a company that continues to innovate and deliver leading-edge IP solutions," adds Rob Dekker, Verific's president. "We're delighted that it selected our SystemVerilog component software to be used in its design flow." About Verific Design Automation Verific Design Automation was founded in 1999 by electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog, VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and PSL/Sugar front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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