DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry's First High-level DFT Sign-off Methodology.

HiDFT-Scan Analyzes, Implements Scan Test Structures in Register-Transfer Level Designs; Closes Historical Gap between RTL and DFT 

PALO ALTO, Calif. -- DeFacTo Technologies today announced a new design for test (DFT) product that analyzes register-transfer level (RTL) integrated circuit and system-on-chip designs, creates appropriate RTL scan test structures, and inserts them into the RTL design. The new product, HiDFT-Scan, works within existing design flows and with industry-standard synthesis tools. Because it eliminates the need for gate-level scan, the new product has enabled chip designers to create the industry's first high-level DFT sign-off methodology.

HiDFT has been used on customer designs in both the U.S. and Europe. Chouki Aktouf, founder and CEO of DeFacTo, said, "For the first time in the EDA industry, designers have a tool that handles RTL scan insertion independently of the synthesis process. The Imaging Division of STMicroelectronics and a major U.S. semiconductor manufacturer have obtained excellent results with HiDFT-Scan in demanding evaluations, and both companies seek to implement a DFT sign-off methodology, fully at RTL."

"Integrating the complete testability at the register-transfer level, including scan, is key to detecting test issues very early in the design phase," said Jocelyn Moreau, DFT manager at STMicroelectronics Imaging Division. "We have run extensive tests of DeFacTo's technology, inserting scan test structures in sophisticated RTL code and mixing VHDL and Verilog. We are pleased with the outcome of those tests and look forward to working with DeFacTo in the future."

HiDFT-Scan addresses a major problem in nanometer electronic circuit design: The ability to fulfill DFT closure requirements at the gate level has come to a standstill. As feature sizes have shrunk, designs have become more complex and the volume of test patterns has increased to the point where it is unrealistic to perform verification tasks at the gate level. At the gate level, any late logic implementation step, including scan, significantly impacts design choices and schedules, and may seriously impact timing, power, and frequency goals.

In contrast, with HiDFT-Scan, designers are able to do the following:

* Create a high-level DFT sign-off methodology - close the gap between RTL and DFT and move toward system-level design.

* Implement all DFT-related logic at the same level where the main design decisions are made - at RTL.

* Identify test issues early.

* Speed RTL simulation and formal verification - run existing simulation on a design after scan is inserted.

* Avoid inserting additional test structures on timing-critical paths post-synthesis.

* Augment existing design sign-off methodologies at RTL using new capabilities such as RTL analysis and management of test power.

"We were impressed with the performance results from HiDFT-Scan on the design of a video decoding chip," said Michael Howard, formerly DFT manager at a major U.S. semiconductor manufacturer. "With our traditional approach using gate-level scan, we had problems completing synthesis without a performance upgrade option. But when we used the RTL code from HiDFT-Scan, we could run standard synthesis with no problems - and we finished several hours earlier. In addition, we had no timing, area, power, or coverage penalties."

Howard continued, "We also appreciated the way HiDFT-Scan generated RTL scan test benches. This allowed us to proceed with both design verification and test related corrections before generating the gate-level netlist. In many cases, the testbenches can be reused after slight design edits - this is not true using the traditional approach. After reviewing the results using FastScan, we found that the HiDFT scan-inserted netlist was entirely consistent with FastScan DFT scan design rules. I am confident that the tool can be used in a production environment."

Specific HiDFT-Scan capabilities include the following:

* Automated generation of final RTL including the scan logic

* Robust set of Design Rule Checks

* Scan verification at RTL through automated generation of testbenches

* Compatibility with all industry-standard synthesis, test compression and ATPG tools and flows

* Compatibility with Verilog 95 and 2001, VHDL, and mixed HDL 

DeFacTo will demonstrate HiDFT-Scan at the International Test Conference (http://www.itctestweek.org/) in Santa Clara, Calif., October 23-25, 2007. To register in advance for a demonstration, go to http://www.defactotech.com.

HiDFT-Scan is available now from DeFacTo Technologies.

About DeFacTo Technologies

DeFacTo is an innovative chip design software company developing breakthrough technology to dramatically enhance the design for test (DFT) process and increase the testability of integrated circuits (ICs) and systems on a chip (SoCs). The company's mission is to enable designers to plan, analyze, and implement IC test logic before synthesis, by delivering a high quality suite of tools working at the RT level, covering all DFT needs. The company, founded in August 2003, is headquartered near Grenoble France, with U.S. headquarters in Palo Alto, Calif. Visit DeFacTo online at http://www.defactotech.com.

NOTE: DeFacTo and HiDFT-Scan are registered trademarks of DeFacTo Technologies Inc. FastScan is a trademark of Mentor Graphics Corporation. Any other trademarks or registered trademarks mentioned in this release are the property of their respective owners.