DVCon 2008 Announces Technical Program.BOULDER, Colo. -- The Design and Verification Conference (DVCon) today announced the 2008 technical program for the annual conference, which will be held February 19-21, 2008 at the DoubleTree Hotel in San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. . In addition to continuing its tradition of providing educational and practical material that can be implemented in today's designs, this year the conference will pay special attention to the verification of low power designs. "This year at DVCon, attendees can look for fresh approaches to design and verification problems," stated Steve Bailey Steve Bailey is a bassist famous for his pioneering work with the six string fretless bass and was voted runnerup for Bass Player Of The Year in 1994 and 1996. He began playing the Bass Guitar at age 12 and began playing fretless bass , general chair of DVCon 2008. "In particular, the growing interest in functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, as a critical discipline for electronic systems design and development will be addressed with sessions on low power design verification, verification methods and formal verification
In the context of hardware and software systems, formal verification ." To read a complete letter from the general chair, please visit http://www.dvcon.org/html/about.html. Highlights of DVCon 2008 This year's conference includes a total of 10 in-depth technical paper sessions, presenting a wide range of topics including verification methodology, formal verification and functional coverage, as well as verification of low-power, multi-clock and analog/mixed-signal systems. There are also several sessions on applications of SystemVerilog and SystemC for verification and an invited session on advances in research from both industry and academia. As always, the first day of the program includes five sponsored half-day tutorials, providing in-depth looks at a variety of state-of-the-art verification topics. These sessions were garnered from a total of 110 submitted abstracts that were reviewed in detail by the Technical Program Committee. Two highlights of the conference will take place on Wednesday, February 20: the keynote address keynote address n. An opening address, as at a political convention, that outlines the issues to be considered. Also called keynote speech. Noun 1. by Dr. Wally Rhines, CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. and Chairman of the Board for Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. Corp., and the annual "Troublemaker's Panel" organized and moderated by John Cooley. Dr. Rhines will be speaking about the complexity challenges in functional verification which are forcing designers to adopt new approaches, as well as the impact these changes will have on engineers. He will address the question, "Will the next advances in verification require engineers to relearn Verb 1. relearn - learn something again, as after having forgotten or neglected it; "After the accident, he could not walk for months and had to relearn how to walk down stairs" much of their approach to design, as they did when schematic capture gave way to hardware description languages, or will these changes be more evolutionary in nature?" DVCon is also the venue that has become well-known for John Cooley's unconventional "Troublemaker's" panel where prominent industry figures are put in the hot seat with unedited questions supplied by the 25,000 members of ESNUG ESNUG E-Mail Synopsys Users Group . On Thursday, attendees will also have the opportunity to attend a panel event called "Driving Design Verification Results: Formal Verification Comes of Age." Speakers will address strategies for eliminating redundant verification efforts, increasing verification productivity and reducing interoperability problems. Panelists will include representatives from Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. , Inc.; IBM (International Business Machines Corporation, Armonk, NY, www.ibm.com) The world's largest computer company. IBM's product lines include the S/390 mainframes (zSeries), AS/400 midrange business systems (iSeries), RS/6000 workstations and servers (pSeries), Intel-based servers (xSeries) , Corp.; Intel, Corp.; Jasper Design Automation, Inc.; and Mentor Graphics, Corp. In addition to a great technical program, DVCon has increased the size of the exhibit floor to accommodate more vendors this year. Hours for the exhibits are Tuesday from 4:30 p.m. to 7:30 p.m. and Wednesday from 4:30 p.m. to 7:30 p.m. It is complimentary registration to attend the exhibits and the pass includes access to the keynote as well as the Troublemakers panel. Full program information is available at the DVCon website (www.dvcon.com). To Register To register for DVCon 2008, go to: http://www.dvcon.com/reg.html or call Nannette Jordan at 303-530-4562. About DVCon DVCon is sponsored by Accellera, an industry consortium dedicated to the development and standardization of design and verification languages. For more information about Accellera, please visit www.accellera.org. |
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