DVCon 2008 Announces Record Exhibitors.Advanced Registration Ends January 23 DENVER -- The 2008 Design and Verification Conference (DVCon) today announced a 30% increase in the exhibitor participation from 2007. DVCon also reminds attendees that the advanced registration discount ends tomorrow - Wednesday, January 23, 2008. DVCon 2008 will be held on February 19-21, 2008 at the DoubleTree Hotel in San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. . Hours for the exhibits are Tuesday, February 19 from 4:30 p.m. to 7:30 p.m. and Wednesday, February 20 from 4:30 p.m. to 7:30 p.m. A complimentary registration to attend the exhibits is available. Highlights of DVCon's 2008 Program Some highlights of the show include: -- The keynote address keynote address n. An opening address, as at a political convention, that outlines the issues to be considered. Also called keynote speech. Noun 1. by Dr. Wally Rhines, CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. and Chairman of the Board for Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. Corp., entitled "Ending Endless Verification." In his keynote address, Dr. Rhines will explore new solutions and innovations in functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, technology and discuss the impact of these changes on the evolution of the EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. industry. The keynote will be delivered Wednesday, February 20 from 2:00 - 2:45 in the Oak/Fir Ballroom. -- The annual "Troublemaker's Panel" organized and moderated by John Cooley, moderator of ESNUG ESNUG E-Mail Synopsys Users Group . The Troublemaker's Panel will be held Wednesday, February 20 from 3:00 - 4:30 in the Oak/Fir Ballroom. -- A panel event entitled "Driving Design Verification Results: Formal Verification
In the context of hardware and software systems, formal verification Comes of Age." At this event, several industry executives will be addressing strategies for eliminating redundant verification efforts, increasing verification productivity and reducing interoperability problems. The panel will be held Thursday, February 21 from 9:00 - 10:00 in the Donner Ballroom. Full program information is available at the DVCon website (www.dvcon.org). To Register To qualify for the reduced rates, registrations must be received prior to the Advanced Registration Deadline on January 23, 2008. A complimentary registration is available to attend the exhibits hall, as well as the keynote and the Troublemakers Panel. To register for DVCon 2008, go to: http://www.dvcon.com/reg.html or call Nannette Jordan at 303-530-4562. About DVCon DVCon is the premier conference for functional design and verification of digital electronic systems. The conference has grown from its days as user groups focused on HDLs to a full-fledged conference, featuring the latest technology, techniques, standards and methods. For more information about DVCon, please visit www.dvcon.org. DVCon is sponsored by Accellera, an industry consortium dedicated to the development and standardization of design and verification languages. For more information about Accellera, please visit www.accellera.org. |
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