DVCon 2007 Announces Call for Paper, Panel and Tutorial Proposals; Deadlines for submissions begin September 19, 2006.BOULDER, Colo. -- The 2007 Design and Verification Conference (DVCon), sponsored by Accellera, is now accepting paper, panel and tutorial submissions. Proposals that reflect real experiences using hardware design and verification languages, advanced tools and methodologies are encouraged. DVCon 2007 will be held February 21-23 at the DoubleTree Hotel in San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. . It is the premier conference focusing on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. . The conference will focus on the use of specialized design and verification languages such as Verilog, SystemVerilog, VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. , PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. SystemC, e, and VERA VERA Virtual Entity of Relevant Acronyms VERA Virtual Electronic Resource Access VERA Vienna Environmental Research Accelerator VERA Verzeichnis Edv-Relevanter Akronyme (German: Virtual Entity of Relevant Acronyms; website) , as well as general purpose languages such as C and C++. All paper, tutorial and panel submissions related to using HDLs, HVLs or other languages used for hardware design or verification will be considered. All topics can be found by visiting www.dvcon.org. Paper and panel proposals are due September 19, 2006 To submit a panel proposal, please email Kathy Embler at MP Associates at kathy@mpassociates.com. Paper proposals must be submitted on-line at www.dvcon.org. Submission site opens on September 1, 2006. Proposals are also being accepted for special sessions and sponsored tutorials. Special sessions may consist of embedded Inserted into. See embedded system. tutorials of one to two hours in length or may be focused on a specific topic with a list of invited papers/presentations relevant to that topic. Special session tutorials proposals must be submitted via email to Kathy Embler at kathy@mpassociates.com. Sponsored tutorials are due October 5, 2006 A limited number of sponsored tutorials will also be available. Proposals are due October 5. To submit sponsored tutorial ideas, please contact Kathy Embler at MP Associates at kathy@mpassociates.com. Accellera sponsors DVCon. Accellera is an industry consortium dedicated to the development and standardization of EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. languages, methods and formats, including design and verification languages. For more information about Accellera, please visit www.accellera.org. |
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