DVCon 2005 Announces Keynote, Sponsored Tutorials and Registration Deadlines.BOULDER, Colo. -- Walden C. Rhines, Chairman and Chief Executive Officer of Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. , Corp., will be the keynote speaker at the 2005 Design and Verification Conference (DVCon) sponsored by Accellera. The conference and exhibition will be held February 14-16 at the DoubleTree Hotel in San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. . Rhines will address "Verification Discontinuities in the Nanometer Age" on Tuesday, February 15 at 8:30 a.m. in the Donner Ballroom. For more information regarding the keynote address keynote address n. An opening address, as at a political convention, that outlines the issues to be considered. Also called keynote speech. Noun 1. , please visit http://www.dvcon.org/keynote.html. Conference Schedule: DVCon 2005 will have four sponsored tutorials on Monday, February 14. The sponsored tutorials are included in the full conference registration fee. For exhibit-only registrants, each tutorial is $50.00: 1. "SystemVerilog Assertions: Best Practices for Functional Verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, " is sponsored by Synopsys, Inc. 2. "Pragmatic ABV ABV Above ABV Alcohol By Volume ABV Abuja, Nigeria (airport code) ABV Assault Breacher Vehicle ABV Accredited Business Valuation specialist ABV Auxiliary Building Ventilation ABV Annual Buy Value ABV Air Bleed Valve : Effective Assertion-Based Verification" is sponsored by Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. , Inc. 3. "Transitioning to SystemVerilog for Verification" is sponsored by Mentor Graphics Corp. 4. "Transaction-Level Modeling Transaction-level modeling (TLM) is a high-level approach to modeling digital systems where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. with the New OSCI SystemC TLM TLM Telemetry TLM Transaction Level Modeling TLM Tout Le Monde (French) TLM The Leprosy Mission (Northern Ireland) TLM Transmission Line Matrix TLM The Little Mermaid (fairy tale) Standard" is sponsored by Cadence Design Systems, Inc. For information regarding the tutorials, please visit http://www.dvcon.org/tutorials.html. On Tuesday, February 15, in addition to the keynote, the technical program will include six technical sessions followed by an executive panel moderated by John Cooley. This exciting panel is open to exhibit-only and full conference registrants. Following the panel, attendees are invited to a reception at 5:00 p.m. that will include all exhibitors. On Wednesday, February 16 there will be three panel sessions, and the conference will conclude with the presentation of Best Paper Award in the Design and Verification areas. Exhibits are open Monday, February 14 from 4:00 p.m. - 7:00 p.m. and Tuesday, February 15 from 9:00 a.m. - 7:00 p.m. For more details about each technical session, tutorial and panel, please visit http://www.dvcon.org/techprog.html. Register by January 18 and save $100 Attendees must register by January 18 to receive a $100 discount on full-conference registration. For more information regarding DVCon registration or to register online, please visit http://www.dvcon.org/reg.html. About DVCon DVCon is focused on the use of Hardware Description Languages and Hardware Verification Languages for the design and verification of electronic systems and ICs. For more information, please visit www.dvcon.org About Accellera For more information, please visit www.accellera.org. |
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