DVCon 2005 Announces Final Program; Cooley's Bigwigs Panel to Pose 'Edgy' Questions; Advanced Registration Closes Monday, February 20.BOULDER, Colo. -- The 2006 Design and Verification Conference (DVCon) will provide attendees with a deeper understanding of how the latest standards ratified by the IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. in record-breaking time, IEEE 1800(TM) SystemVerilog, IEEE 1666(TM) SystemC, and IEEE 1850(TM) PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. , can aid in the quest for Verb 1. quest for - go in search of or hunt for; "pursue a hobby" quest after, go after, pursue look for, search, seek - try to locate or discover, or try to establish the existence of; "The police are searching for clues"; "They are searching for the better productivity and cost savings in design and verification. Online registration is available through Monday, February 20, 2006. Registration after Monday can be done on-site. The conference and exhibition will be held February 22-24 at the DoubleTree Hotel in San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. . For conference and registration information, please visit www.dvcon.org. Conference Highlights: There is no charge for the keynote address keynote address n. An opening address, as at a political convention, that outlines the issues to be considered. Also called keynote speech. Noun 1. , the John Cooley panel, and the cocktail reception. These events are open to the industry but attendees must register. Keynote Address: This year's keynote address, titled "Skyscrapers and Chip Design," will be delivered by John Chilton John James Chilton (born 16 July 1932 in London, England) is a British jazz trumpeter and writer. During the 1960s he also worked with pop bands, including the Swinging Blue Jeans. , Senior Vice President and General Manager of Synopsys' Solutions Group, at 2:00 p.m. on Thursday, February 23 in the Fir Ballroom. In his keynote Chilton will share insights on design productivity based on data gathered from real design projects. Many managers believe that the key to better productivity lies primarily in the quality of the tools, but that's not the whole story. Join us to better understand the influencers of design productivity -- some the audience will recognize, others may come as a surprise. John Cooley's "Bigwigs" panel: Now an annual event, John Cooley will be asking executives edgy questions provided by his readership during his infamous Bigwigs panel on Thursday, February 23 beginning at 3:30 p.m. in the Fir Ballroom. Top-level executives on this year's panel include: Rajeev Madhavan - Chairman & CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Magma; Antun Domic - Sr. VP & GM, Implementation, Synopsys; Joe Sawicki - VP & GM, Design-to-Silicon, Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. ; Ted Vucurevich - Sr. VP & CTO (Chief Technical Officer) The executive responsible for the technical direction of an organization. See CIO and salary survey. , Advanced R&D, Cadence; Atul Sharan - President & CEO of Clear Shape; Kathryn Kranen - President & CEO of Jasper; Brett Cline - "The SystemC Poster Boy"; and Gary Smith - Managing VP Design & Engineering, Gartner Dataquest. A cocktail reception will immediately follow the panel. Sponsored Tutorials: There are four sponsored tutorials this year. Cadence: "Deploying SystemVerilog on Your Next project"; Synopsys and Arm: "Using the Verification Methodology Manual for SystemVerilog"; Mentor: "TLM TLM Telemetry TLM Transaction Level Modeling TLM Tout Le Monde (French) TLM The Leprosy Mission (Northern Ireland) TLM Transmission Line Matrix TLM The Little Mermaid (fairy tale) and Advanced Verification: A Methodology for Quickly Constructing Re-usable Transaction-Based Testbench Environments in SystemVerilog and SystemC"; and Synopsys: "SystemVerilog Assertions: From Concept to Practice." For more information on the technical program and schedule, please visit: http://www.dvcon.com/techprog.html. Exhibit Hours Exhibits are open Wednesday, February 22, and Thursday, February 23, from 4:00 p.m. - 7:00 p.m. A list of exhibiting companies is available at: http://www.dvcon.com/exlist.html. About DVCon DVCon is sponsored by Accellera, an industry consortium dedicated to the development and standardization of design and verification languages. For more information about Accellera, please visit www.accellera.org. For more information about DVCon, please visit www.dvcon.org. |
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