DVCon 2004 Announces Final Program with Ray Bingham to Provide Keynote.Business Editors 2004 Design and Verification Conference BOULDER, Colo.--(BUSINESS WIRE)--Feb. 11, 2004 Conference to serve as a platform for discussion of hardware design and verification issues and challenges facing design engineers Ray Bingham, president and chief executive officer of Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. , Inc., will be the keynote speaker at the 2004 Design and Verification Conference (DVCon) sponsored by Accellera. The conference and exhibition will be held March 1-3, 2004, at the DoubleTree Hotel in San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. . Bingham's keynote, "Making Design and Verification a Strategic Business Asset" will discuss his vision for taking the industry to the next level by providing valuable insight into the important role business transformation plays in the development and proliferation of technology and new products. The keynote address keynote address n. An opening address, as at a political convention, that outlines the issues to be considered. Also called keynote speech. Noun 1. will be on Tuesday, March 2 at 8:30 a.m. in the Donner Ballroom at the DoubleTree Hotel in San Jose San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. . Conference Schedule: On Monday, March 1, 2004, there will be six half-day tutorials. There are two promotional tutorials this year that are included in the full conference registration fee. "Using PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. with HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. for Formal and Dynamic Verification" is sponsored by Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. and "System Design and Verification Using SystemC and SCV SCV Santa Clarita Valley (California) SCV Sons of Confederate Veterans SCV Santa Clara Vanguard SCV Singapore Cable Vision SCV Special Category Visa (Australia) SCV StarHub Cable Vision " is sponsored by OSCI. The conference fee is $50.00 per promotional tutorial for exhibit-only registrants. On Tuesday, March 2, in addition to the keynote, the technical program will include four technical sessions followed by a "Talking Heads" panel. The panel will feature key industry executives discussing current industry issues such as the off-shoring of US design jobs, whether or not there's an RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; synthesis war brewing, the reality of System Verilog, etc. John Cooley will moderate the panel. This exciting panel is open to exhibit-only and full conference registrants. Following the panel, attendees are invited to a reception at 5:00 p.m. that will include all 19 exhibitors. On Wednesday, March 3, there will be three panel sessions, including a luncheon panel sponsored by Jasper Design Automation titled, "Next Generation Verification: Addressing the Challenges of Better Design Quality and Shorter Schedules." There will also be four technical sessions, as well as the exhibits that day. For more details about each technical session, tutorial and panel, please visit http://www.dvcon.com/techprog.html Best Paper Award: Conference attendees will be given the opportunity to select this year's best paper awards. Winners for Best Design Paper and Best Verification Paper will each receive $1,000. About DVCon DVCon is focused on the use of Hardware Description Languages and Hardware Verification Languages for the design and verification of electronic systems and ICs. For more information, please visit www.dvcon.org About Accellera For more information, please visit www.accellera.org. |
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