Cypress Taps Aldec for Full Timing Simulation in Warp2 Software; Finite State Machine Editor Also Added to Popular $99 Package.

SAN JOSE, Calif.--(BUSINESS WIRE)--June 15, 1998--Cypress Semiconductor Corp. (NYSE:CY) today announced that it has signed a letter of intent with Aldec, Inc. to include timing simulation and Finite State Machine (FSM) editing in its Warp2(TM) programmable logic software tool.

Cypress will include these new features from Aldec's Active-VHDL(TM) in an upcoming Warp2 release at no additional cost to customers, maintaining its market leading $99 price for the software package.

Cypress recently announced its Ultra37000(TM) family of CPLDs, which includes a 512-macrocell device. Cypress is also planning a new family for introduction later in the year that will offer even larger densities.

"As designs become more complex, post-synthesis simulation gives users the opportunity to easily check their system timing and functionality to ensure they are on track," said Christopher Norris, vice president of Cypress's Programmable Logic Division. "Adding the Aldec solution to our existing Warp synthesis technology allows us to support these larger designs with the highest performance products at market-leading prices."

"Aldec recognizes that Cypress is an innovator in low-cost HDL-based solutions. This relationship fits directly into Aldec's overall marketing strategy of 'HDL for the masses,' and will provide all Cypress Warp users with a completely integrated solution and HDL-based simulation technology," said Stanley Hyduke, president of Aldec.

As part of this relationship, Cypress will have direct access to two of Aldec's proven HDL solutions: the Finite State Machine Editor, which enables graphical design entry and automatic HDL generation; and timing simulation based on a structural VHDL netlist for post fitting simulation. The simulation technology being utilized by Cypress is a subset of the complete Active-VHDL product and will enable timing simulation for Cypress device families only. The subset offers a seamless upgrade path to Aldec's complete product offering which will enable behavioral VHDL simulation, automatic testbench generation and access to Aldec's cores.

Cypress is the only vendor to write its own HDL synthesis, and therefore Warp(TM) software delivers performance results that are unrivaled in the industry. At the same time, Cypress charges only $99 for the Warp2(TM) tool, selling it over the Internet and through toll-free phone lines in the U.S. Warp software supports Cypress's In-System Reprogrammable (ISR(TM)) CPLDs - the Ultra37000(TM) and FLASH370iO families - as well as a broad array of SPLDs.

Aldec, Inc., headquartered in Henderson, Nevada, produces a universal suite of Windows-based EDA tools that allow design engineers to implement their designs using several different design entry methods (schematic capture, state machine, VHDL, Verilog, or ABEL). Active-CAD(TM) and Active-VHDL(TM) incorporate patented simulation technology and several design entry tools that provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the Windows-based EDA market as the fastest growing, privately held EDA supplier in the world. Additional information about Aldec is available at www.aldec.com.

Cypress Semiconductor Corporation is an international supplier of high-performance integrated circuits with worldwide headquarters in San Jose, California. The company provides a broad range of products for leading computer, networking, and telecommunications companies worldwide. Cypress's product line includes static RAM and specialty memories; programmable logic devices (PLDs); data communications products; FCT logic; and personal computer timing devices and USB microcontrollers. Its shares are listed on the New York Stock Exchange under the symbol CY. The company's worldwide web site is http://www.cypress.com.

NOTE TO EDITORS: Warp, Ultra37000, FLASH370i, and ISR are trademarks, and Warp2 is a registered trademark of Cypress Semiconductor. Active-VHDL and Active-CAD are trademarks of Aldec, Inc.

CONTACT: Cypress Semiconductor

Don Parkman, 408/943-2817

or

Aldec

David Rinehart, 702/456-1222