Cypress Introduces Next-Generation QuadPort Datapath Switching Element -- DSE -- Family.Business Editors/High-Tech Writers SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 30, 2002 High-Performance Devices Target High-End Wireless Basestation, Storage Subsystem and WAN Switch Applications Cypress Semiconductor Corporation (NYSE NYSE See: New York Stock Exchange :CY) today introduced its next-generation high-performance QuadPort(R) Datapath Switching Element (DSE 1. DSE - Display Screen Equipment. See Visual Display Unit. 2. DSE - Data Structure Editor. ), which supports bandwidths up to 27 Gigabits per second (Gbps) and provides densities up to 5 Mbits. Cypress's QuadPort DSE is a four-port switching element that allows simultaneous access to an integrated memory array from each of its completely independent ports which can operate in different frequency domains. The family can help eliminate contention and arbitration issues on a shared bus when multiple processors or functional blocks need access to the same data, thereby significantly improving overall system performance. Cypress pioneered the concept of QuadPort DSEs with the introduction of its one Mbit family (10 Gbps bandwidth) in 2001, including functions such as 2 x 2 switching, datapath aggregation, redundant data generation and packet header manipulation. This next-generation QuadPort DSE family adds higher bandwidth (4 ports x 167 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. x 40 bits) and higher storage capacity (up to 5Mbits). At these unprecedented levels of performance and storage, Cypress doubles the bandwidth and over quadruples the density of any competitive offerings. "These high-performance devices put Cypress a generation ahead of the competition and allow our customers to create innovative system architectures, thereby achieving higher performance and efficiency," said Geoff Charubin, marketing director for Cypress's Data Communications Division. "By providing up to 5 Mbits of integrated memory at 27 Gbps operation, the QuadPort DSE enables our customers to reduce the need for multiple devices, thereby significantly improving their cost-per-megabit of capacity and cost-per-gigabit of bandwidth." QuadPort DSE Innovates System Architecture The QuadPort DSE shows its strength as a communications datapath enabler because its combination of logic and memory creates a non-blocking switch architecture. Maximum system benefit is gained by planning for usage during the architectural stage of design. For example, the devices may be used as -- a 2 x 2 switch fabric among four devices such as field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), application specific integrated circuits (ASICs), PHYs or a series of digital signal processors (DSPs) -- a data-path aggregator that allows multiplexing multiple low-bandwidth data streams into a single high-bandwidth data stream -- a redundant data-path generator that allows users to input a single stream of data into one port and then output identical data streams at variable data rates on each of the other ports for fault tolerance and parallel processing -- a packet-header manipulation engine that uses two ports to read and write an entire packet and one or two ports to monitor and/or change the header, which provides an alternative for high-cost data-path FPGAs by lowering its logic-gate count, I/O number, and internal memory requirements. When used in conjunction with the Cypress OC-48 port SERDES See serializer/deserializer. , Delta39K(TM) CPLDs and HOTLink hotlink - A mechanism for sharing data between two application programs where changes to the data made by one application appear instantly in the other's copy. Under System 7 on the Macintosh the users establishes a hotlink by doing a "Create Publisher" on the server and (R) family of backplane physical-layer devices, the QuadPort DSE family provides a complete system solution for customers building communications linecards. Communications systems customers who are already familiar with Cypress's Quad Data Rate Quad data rate (or quad pumping) is a communication signalling technique wherein data is transmitted at both the rising and falling edges of the clock signal, much the same way DDR technology works, but with two clock signals 90° out of phase from each other, effectively (TM) RAM, BEAST(TM) FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods. FIFO - first-in first-out , synchronous SRAM See static RAM. SRAM - static random-access memory , CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. , and clock solutions will also benefit from the QuadPort DSE Family. QuadPort DSE Features This QuadPort DSE family of devices offers configurable I/Os supporting LVTTL LVTTL Low Voltage Transistor Transistor Logic (AMCC) LVTTL Low Voltage Transistor to Transistor Logic and SSTL SSTL Surrey Satellite Technology Ltd SSTL Stub Series Terminated Logic SSTL Site Specific Target Level SSTL Solid State Track Link 2 standards, enabling seamless interface with PLDs, FPGAs, ASICs, next-generation DSPs, control processors and other memory devices on the board. These devices also come with advanced features such as impedance matching on data outputs to reduce transmission line effects; burst counters for enabling block transfer of data; and memory block retransmit for rereading a block of data in case of transmission failure. All QuadPort DSEs offer four completely independent ports that can simultaneously access the data storage array and operate in different frequency domains. Each port can read or write data up to 167 MHz, giving the device up to 27 Gbps of data throughput or bandwidth. Offered in a 676-ball PBGA PBGA Plastic Ball Grid Array package measuring 27 mm x 27 mm with a 1.0 mm pitch, these devices are compliant with IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 1149.1 JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group boundary scan for a high degree of manufacturability.
Availability and Price
Bandwidth Data Storage Max. Part Number Availability Pricing
Capacity Frequency (10K
volumes)
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27 Gbps 64 Kbits x 40 167 MHz CY7C0451V18 End 4Q02 $115.00
(2.5 Mbit)
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27 Gbps 32 Kbits x 40 167 MHz CY7C0450V18 1Q03 $80.00
(1.3 Mbit)
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13 Gbps 128 Kbits x 20 167 MHz CY7C0431V18 1Q03 $115.00
(2.5 Mbit)
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13 Gbps 64 Kbits x 20 167 MHz CY7C0430V18 1Q03 $80.00
(1.3 Mbit)
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27 Gbps 128 Kbits x 40 167 MHz CY7C0452V18 2Q03 $138.00
(5 Mbit)
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Photo A high-resolution photo of the QuadPort DSE can be downloaded from http://www.cypress.com/pub/cy7c0451v18.jpg. About Cypress Cypress Semiconductor Corporation (NYSE: CY) is Connecting From Last Mile to First Mile(TM) with high-performance solutions for personal, network access, enterprise, metro switch and core communications-system applications. Cypress Connects(TM) using wireless, wireline, digital and optical transmission standards, including Bluetooth, USB USB in full Universal Serial Bus Type of serial bus that allows peripheral devices (disks, modems, printers, digitizers, data gloves, etc.) to be easily connected to a computer. , Fibre Channel, SONET/SDH, Gigabit Ethernet and DWDM (Dense WDM) The term given to wavelength division multiplexing (WDM) when significantly more channels were being added. Since WDM is increasingly more "dense" all the time, both terms are used synonymously. See WDM. DWDM - wavelength division multiplexing . Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions and programmable microcontrollers. More information about Cypress is available online at www.cypress.com. "Safe Harbor" Statement under the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and of 1995: Statements herein that are not historical facts are "forward-looking statements" involving risks and uncertainties, including but not limited to: the effect of global economic conditions, shifts in supply and demand, market acceptance, the impact of competitive products and pricing, product development, commercialization and technological difficulties, and capacity and supply constraints. Please refer to Cypress's Securities and Exchange Commission filings for a discussion of such risks. Cypress, the Cypress logo, HOTLink and QuadPort are registered trademarks, and "Connectivity From Last Mile to First Mile," "Cypress Connects," Delta39K and BEAST are trademarks, of Cypress Semiconductor Corporation. QDR QDR Quadrennial Defense Review (US DoD) QDR Quad Data Rate (Memory Technology) QDR Quality Deficiency Report QDR Quality, Durability and Reliability (Toyota Motor Company) and Quad Data Rate are trademarks of the QDR Consortium. |
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