Cypress Introduces Industry's First Complete Data Transport Solution Featuring Transparent Generic Framing Procedure.Business Editors/High-Tech Writers SAN JOSE, Calif.--(BUSINESS WIRE)--March 24, 2003 MetroLink(TM) Link-Layer Device is the Final "Link" in System-Level Solutions for Next-Generation ADMs, MSPPs and DWDM (Dense WDM) The term given to wavelength division multiplexing (WDM) when significantly more channels were being added. Since WDM is increasingly more "dense" all the time, both terms are used synonymously. See WDM. DWDM - wavelength division multiplexing Equipment for the Metro Cypress Semiconductor Corporation (NYSE NYSE See: New York Stock Exchange :CY) today announced the availability of its MetroLink2T-2(TM) (CYL CYL Cylinder CYL See You Later CYL Catch You Later CYL Complex Stutter Dial Report CYL See Y'all Later CYL Call Your Lawyer 2T0201) link-layer device (LLD LLD abbr. Latin Legum Doctor (Doctor of Laws) LLD Doctor of Laws [Latin Legum Doctor] Noun 1. ) -- the first LLD on the market to offer transparent generic framing procedure Generic Framing Procedure (GFP) is defined by ITU-T G.7041. This allows mapping of variable length, higher-layer client signals over a transport network like SDH/SONET. The client signals can be protocol data unit (PDU) oriented (like IP/PPP or Ethernet Media Access Control) or can (GFP-T GFP-T Transparent Generic Framing Protocol ). MetroLink2T-2 LLD is an intellectual property (IP) core that enables efficient mapping of packet data over synchronous data transmission on optical media (SONET) backbones. The Cypress GFP-T transport core supports two channels of Gigabit Ethernet (GbE), Fibre Channel, Enterprise Systems Connection (ESCON (Enterprise Systems CONnection) An IBM S/390 fiber-optic channel that transfers 17 Mbytes/sec over distances up to 60 km depending on connection type. ESCON allows peripheral devices to be located across large campuses and metropolitan areas. ), Fibre Connectivity (FICON (FIber CONnector) An IBM mainframe channel introduced with its G5 servers in 1998. Based on the Fibre Channel standard, it boosts the transfer rate of ESCON's half-duplex 17MB/sec to a full-duplex 100MB/sec. ), or any combination of protocols over SONET. In addition, Cypress has leveraged its virtual concatenation (VC) expertise along with GFP-T features for efficient bandwidth management. The introduction of MetroLink2T-2 LLD demonstrates Cypress's commitment to providing its customers with complete solutions for building communications linecards. By teaming MetroLink2T-2 LLD with other Cypress transport products -- POSIC POSIC Partially-Connected Ordered Successive-Interference Cancellation 2GVC(TM) OC-48/STM-16 Framer, HOTLink II(TM) transceiver, No Bus Latency(TM) (NoBL(TM)) synchronous SRAM See static RAM. SRAM - static random-access memory , ComLink(TM) bus interface, and programmable clocks -- the entire linecard datapath incorporates Cypress's products, forming a seamless system solution and eliminating the need for additional external logic. "By adding the MetroLink LLD family to our data communications product portfolio, we are able to provide a complete solution for the packet-over-SONET transport problem," said Christopher Norris, vice president of Cypress's data communications division. "Our system-level solution is logically partitioned for easy design migration. This allows our customers to develop derivative linecards while re-using portions of the design, thereby significantly reducing design time, time-to-market and cost." The MetroLink(TM) Family MetroLink2T-2 LLD is the first member of Cypress's MetroLink LLD family of link-layer products. MetroLink2T-2 LLD is also the first product to support GFP-T at OC-48/STM-16 rates. GFP-T is a way to encapsulate any protocol for transport over a SONET/SDH network. Using the MetroLink2T-2 LLD with GFP-T, a carrier can efficiently transport any data over standard SONET/SDH networks with no degradation of service, no waste of bandwidth, and no additional FPGAs or external logic. The POSIC2GVC Framer The POSIC2GVC OC-48/STM-16 framer is a revolutionary product able to provide virtual concatenation per ITU G.707. Using VC, the product enables efficient bandwidth utilization and dynamic bandwidth allocation Dynamic Bandwidth Allocation (DBA) is a technique by which traffic bandwidth in a shared telecommunications medium can be allocated on demand and fairly between different users of that bandwidth. . Furthermore, embedded packet preclassification functions allow increased packet processing, quality of service (QoS) control, and queue management performance. In addition, POSIC2GVC also transports asynchronous transfer mode See ATM. (communications) Asynchronous Transfer Mode - (ATM, or "fast packet") A method for the dynamic allocation of bandwidth using a fixed-size packet (called a cell). See also ATM Forum, Wideband ATM. ATM acronyms. Indiana acronyms. (ATM) cells across SONET networks. HOTLink II Physical-Layer Devices The HOTLink II family of physical-layer devices offers the industry's most flexible transceivers, with advanced features such as the widest operating range (0.2-1.5 Gbps), channel-to-channel and chip-to-chip channel bonding, by passable 8B/10B encoding, redundant dual outputs, and up to 100K gates of programmable logic. This successful family of devices includes single-channel, dual-channel, quad-channel, independent channel, and Gigabit Ethernet/Fibre Channel versions. No Bus Latency (NoBL) SRAM NoBL synchronous SRAMs have an architecture optimized for the most demanding high-speed applications requiring maximum bus bandwidth, such as networking, test and measurement instrumentation, video, and simulation. Available in both flow-through and pipelined versions, they eliminate the latency (dead cycles or wait states) found in conventional synchronous burst SRAM architectures when transitioning between write and read operations. By contrast, the NoBL architecture allows data transfer on every clock cycle regardless of whether a write or read operation is taking place, thereby providing 100% bus utilization. ComLink Bus Interface and Backplane Chips The ComLink series operates at data transfer rates up to 1.6 Gbps and includes multiplexed-differential line drivers that provide redundant links for serial backplanes, 20-bit wide, three-state buffers, and clock distribution buffers with fanouts of 1:10, 1:8 and 1:4. These devices offer configurable inputs that match industry-standard interfaces including low-voltage CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. (LVCMOS LVCMOS Low Voltage Complementary Metal Oxide Semiconductor LVCMOS Low-Voltage Complementary Metal-Oxide Semiconductor (family of logic integrated circuits) LVCMOS Low Voltage Cmos ), low-voltage differential signaling Low-voltage differential signaling, or LVDS, is an electrical signaling system that can run at very high speeds over cheap, twisted-pair copper cables. It was introduced in 1994, and has since become very popular in computers, where it forms part of very high-speed networks (LVDS (Low Voltage Differential Signaling) A transmission method for sending digital information. LVDS sends data over data high and data low lines rather than data and ground. ), and regular differential (complementary I/O signal pair). The LVDS output drivers are configurable to support standard drive (1.2-ns rise and fall times) and high drive (less than 500-ps rise and fall times). Programmable Clocks Programmable timing solutions combine the convenience of field programmability with the high performance customers have come to expect from Cypress's timing products -- at a cost that is competitive with custom clocks at equivalent volumes. Not only can designers select output frequencies, our CyClocks(TM) and CyClocksRT(TM) software also enables users to optimize device parameters such as drive strength, phase-locked loop bandwidth, and crystal input capacitive loading so that each programmed device can be optimized for a specific board layout. Product Availability and Pricing The MetroLink2T-T (CYL2T0201) netlist is available now starting at $20,000. The CYL2T0201 source code is also available for an additional cost. The complete Cypress GFP-T transport solution, including all components, is in production now. Contact Cypress sales representatives near you for further information on pricing and solution documentation. For more information, go to the Cypress website at http://www.cypress.com/products/datasheet.cfm?partnum=CYL2T0201-AIP. About Cypress Cypress Semiconductor Corporation (NYSE:CY) is Connecting From Last Mile to First Mile(TM) with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress Connects(TM) using wireless, wireline, digital, and optical transmission standards, including USB USB in full Universal Serial Bus Type of serial bus that allows peripheral devices (disks, modems, printers, digitizers, data gloves, etc.) to be easily connected to a computer. , Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and programmable microcontrollers. More information about Cypress is accessible online at www.cypress.com. "Safe Harbor" Statement under the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and of 1995: Statements herein that are not historical facts are "forward-looking statements" involving risks and uncertainties, including but not limited to: the effect of global economic conditions, shifts in supply and demand, market acceptance, the impact of competitive products and pricing, product development, commercialization and technological difficulties, and capacity and supply constraints. Please refer to Cypress's Securities and Exchange Commission filings for a discussion of such risks. Note to Editors: Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. MetroLink, MetroLink2T-2, ComLink, HOTLink, HOTLink II, POSIC2GVC, No Bus Latency, NoBL, CyClocks, CyClocksRT, "Connectivity From Last Mile to First Mile," and "Cypress Connects" are trademarks of Cypress. All other trademarks are the property of their respective owners. |
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