Cypress Hosts Net Seminar Series on High-Speed Clock Design; Trio of Seminars are Available on Demand and can be Viewed at any Time.Business Editors/High-Tech Writers SAN JOSE, Calif.--(BUSINESS WIRE)--Dec. 18, 2003 Cypress Semiconductor Corporation (NYSE NYSE See: New York Stock Exchange :CY) today announced that its Timing Technology Division will host a series of one-hour web seminars concentrating on key issues involved in designing with high-speed clocks. Each seminar is available on demand and may be viewed at any time by accessing the corresponding URL URL in full Uniform Resource Locator Address of a resource on the Internet. The resource can be any type of file stored on a server, such as a Web page, a text file, a graphics file, or an application program. . Presented by Cypress timing technology experts, the seminars will cover a myriad of clock related topics including: architecture basics; power supply bypass and layout considerations for minimal jitter A flicker or fluctuation in a transmission signal or display image. The term is used in several ways, but it always refers to some offset of time and space from the norm. For example, in a network transmission, jitter would be a bit arriving either ahead or behind a standard clock cycle ; system considerations, including cascading PLLs, EMI (ElectroMagnetic Interference) An electrical disturbance in a system due to natural phenomena, low-frequency waves from electromechanical devices or high-frequency waves (RFI) from chips and other electronic devices. Allowable limits are governed by the FCC. , and probing high-speed clocks; and programmable clocks. Timing device parameters, especially phase-locked loop-based clock buffers, have become ubiquitous in high-frequency complex systems. However, how data sheets specify device performance hasn't been improved in the last ten years. Seminar #1, entitled "Evaluating Clock Performance by Its Total Timing Budget Window", presents a more precise measurement of how a clock buffer impacts system-timing budget and the major environmental factors affecting that parameter. To view seminar #1 go to http://www.netseminar.com/nss/showSeminar?sem_num=642. Seminar #2, entitled "Minimizing Total Timing Budget Impact", examines the detailed considerations a designer must make to minimize the Total Timing Budget impact with a clock distribution buffer by using common clock tree examples. To view seminar #2 go to http://www.netseminar.com/nss/showSeminar?sem_num=650. Lastly, Seminar #3, entitled "Total Timing Budget Over a Clock Tree: Reading Between the Datasheets" discusses considerations and examples for designing with cascading phase-locked loops, tracking skew (1) The misalignment of a document or punch card in the feed tray or hopper that prohibits it from being scanned or read properly. (2) In facsimile, the difference in rectangularity between the received and transmitted page. , jitter transference TRANSFERENCE, Scotch law. The name of an action by which a suit, which was pending at the time the parties died, is transferred from the deceased to his representatives, in the same condition in which it stood formerly. , and accumulated jitter. To view seminar #3 go to http://www.netseminar.com/nss/showSeminar?sem_num=655. About Cypress Cypress Semiconductor Corporation (NYSE:CY) is Connecting From Last Mile to First Mile(TM) with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress Connects(TM) using wireless, wireline, digital, and optical transmission standards, including USB USB in full Universal Serial Bus Type of serial bus that allows peripheral devices (disks, modems, printers, digitizers, data gloves, etc.) to be easily connected to a computer. , Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM (Dense WDM) The term given to wavelength division multiplexing (WDM) when significantly more channels were being added. Since WDM is increasingly more "dense" all the time, both terms are used synonymously. See WDM. DWDM - wavelength division multiplexing . Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and reconfigurable mixed-signal arrays. More information about Cypress is accessible online at www.cypress.com. Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. "Connectivity From Last Mile to First Mile" and "Cypress Connects" are trademarks of Cypress. All other trademarks are the property of their respective owners. |
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