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Cypress FailSafe Buffers Relieve Master Clock Failure Problems.


Business Editors/High-Tech Writers

SAN JOSE San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850.
, Calif.--(BUSINESS WIRE)--July 21, 2003

Uninterruptible Clock Devices Target Storage Area Networks,

Wireless Basestations Requiring Clock Redundancy Solutions

Cypress Semiconductor Cypress Semiconductor is a semiconductor design and manufacturing company. It began operations in 1982 and listed publicly in 1986. Two years later, the company shifted over to the New York Stock Exchange under the symbol, (NYSE: CY).  Corporation (NYSE NYSE

See: New York Stock Exchange
:CY), a world leader in timing-technology solutions, today announced availability of two FailSafe(TM) buffers (CY23FS04 and CY23FS08). FailSafe buffers provide an uninterruptible clock source for applications such as storage area networking or wireless basestations where continuous operation of the system is required to maintain mission-critical data in the event of a primary reference clock failure.

The unique FailSafe architecture allows for two user-selectable redundancy options: smooth switching to a secondary reference clock or maintaining the frequency of the failed primary reference clock as long as the power supply is operational. In addition, the devices add another layer of redundancy by providing continuous clock outputs even when both the primary and secondary reference clock fail.

FailSafe buffers rely on an internal digitally-controlled crystal oscillator (DCXO DCXO Digitally-Compensated Crystal Oscillator ), which serves as the back-up clock source and drives the output signals. The DCXO maintains the last frequency and phase information from the reference clock prior to interruption; once the external clock source is restored, the DCXO automatically resynchronizes with minimal phase error. Because the outputs are driven primarily by the DCXO circuit, and only indirectly through the reference clock, FailSafe buffers completely eliminate the abrupt phase changes that typically occur when the user switches between two asynchronous Refers to events that are not synchronized, or coordinated, in time. The following are considered asynchronous operations. The interval between transmitting A and B is not the same as between B and C. The ability to initiate a transmission at either end.  reference clock sources.

"FailSafe buffers provide a simple and reliable method for clock redundancy and smooth switching in a variety of applications that handle mission-critical data," said Tunc Cenger, marketing manager for Cypress's Timing Technology Division. "In addition, the CY23FS04 and CY23FS08, with their dynamically-controlled DCXO circuit, significantly reduce the jitter A flicker or fluctuation in a transmission signal or display image. The term is used in several ways, but it always refers to some offset of time and space from the norm. For example, in a network transmission, jitter would be a bit arriving either ahead or behind a standard clock cycle  of the incoming reference clock. Finally, selectable frequency multiplication and division options complement the rich feature set to create the ultimate clock distribution device for systems with redundancy needs."

FailSafe's internal DCXO allows the user to define a tracking window or range for reference clock phase variations. This dynamic tuning range can be set to limit excessive input timing variations, such as jitter, as the signal is distributed in the system. The elimination of such variations leads to more accurate timing topologies, which are therefore capable of operating at higher frequencies.

The CY23FS04 is a 2.5 V or 3.3 V, 170 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc.  zero-delay buffer with two reference clock inputs and four phase-aligned outputs. The CY23FS08 is a 2.5 V or 3.3 V, 200 MHz zero-delay buffer with two reference clock inputs and eight phase-aligned outputs, which can be configured to run at an integer multiple or factor of the reference frequency.

Pricing and Availability

The CY23FS04 is available now in a space-saving 16-pin TSSOP TSSOP Thin Shrink Small Outline Package
TSSOP Thin Scale Small Outline Package
 package. The CY23FS08 is available now in a 28-pin SSOP SSOP Shrink Small Outline Package
SSOP Sanitation Standard Operating Procedures (USDA)
SSOP Sanitary Standard Operating Procedures
SSOP Sharescan-Open Platform (Ecopy)
SSOP Site Security Operational Procedures
 package. Prices range from $4.35 to $6.55 per unit in 25,000 unit quantities.

For more information on FailSafe products, visit the Cypress website at http://www.cypress.com/products/family.cfm?objectID=failsafe.

Photo

A high-resolution photo of the FailSafe products is available at http://www.cypress.com/support/link.cfm?mr=failsafe.

About Cypress

Cypress Semiconductor Corporation (NYSE:CY) is Connecting From Last Mile to First Mile(TM) with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress Connects(TM) using wireless, wireline, digital, and optical transmission standards, including USB USB
 in full Universal Serial Bus

Type of serial bus that allows peripheral devices (disks, modems, printers, digitizers, data gloves, etc.) to be easily connected to a computer.
, Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM (Dense WDM) The term given to wavelength division multiplexing (WDM) when significantly more channels were being added. Since WDM is increasingly more "dense" all the time, both terms are used synonymously. See WDM.

DWDM - wavelength division multiplexing
. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and programmable microcontrollers. More information about Cypress is accessible online at www.cypress.com.

"Safe Harbor Safe Harbor

1. A legal provision to reduce or eliminate liability as long as good faith is demonstrated.

2. A form of shark repellent implemented by a target company acquiring a business that is so poorly regulated that the target itself is less attractive.
" Statement under the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and  of 1995: Statements herein that are not historical facts are "forward-looking statements" involving risks and uncertainties, including but not limited to: the effect of global economic conditions, shifts in supply and demand, market acceptance, the impact of competitive products and pricing, product development, commercialization and technological difficulties, and capacity and supply constraints. Please refer to Cypress's Securities and Exchange Commission filings for a discussion of such risks.

Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. "Connecting From Last Mile to First Mile," "Cypress Connects" and FailSafe are trademarks of Cypress. All other trademarks are the property of their respective owners.
COPYRIGHT 2003 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2003, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Geographic Code:1USA
Date:Jul 21, 2003
Words:724
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