Cypress Expands IP Oasis Program by Partnering With Eureka Technology; Eureka Technology IP Cores Will be Optimized for Use With Warp Design Tool.Business Editors/High-Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--Nov. 20, 2000 Cypress Semiconductor Cypress Semiconductor is a semiconductor design and manufacturing company. It began operations in 1982 and listed publicly in 1986. Two years later, the company shifted over to the New York Stock Exchange under the symbol, (NYSE: CY). (NYSE NYSE See: New York Stock Exchange : CY) and Eureka Technology today announced an agreement that would make Eureka Technology intellectual property (IP) cores available for licensing as optimized netlists for use in the Cypress Delta39K(TM) family of complex programmable logic devices (CPLDs). Optimized Eureka netlists for Cypress Delta39K programmable devices will further simplify the integration of the CPLDs into system designs and dramatically accelerate time-to-market for applications in the high-growth data communications data communications, application of telecommunications technology to the problem of transmitting data, especially to, from, or between computers. In popular usage, it is said that data communications make it possible for one computer to "talk" with another. , telecommunications, computation and consumer markets. Providing flexibility and time-to-market advantages, programmable logic devices (PLDs) have emerged as viable, cost-effective alternatives to FPGAs. The complexity, integration and functionality of today's PLDs allow designers to place entire digital subsystems on a single device. In addition, designers can make key system changes late in the development cycle, avoiding costly and time-consuming silicon re-spins. The Eureka IP cores targeted to Cypress CPLDs, with corresponding netlists, will be optimized for use in Cypress's HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. based Warp(TM) design tool. Warp is a design solution that integrates graphical capture, simulation, synthesis, and management, replacing the traditional multi-vendor, multi-tool approach to programmable logic device design. "Developing partnerships with IP vendors like Eureka Technology allows our customers to take full advantage of the Delta39K architecture in a short amount of time, enabling them to meet the narrow market windows in the communications arena," said Geoff Charubin, Cypress director of marketing. "The Delta39K family is the first CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. to offer IP, and the Eureka netlists will move us further along in our strategy to provide our customers with a total design solution." "This partnership with Cypress Semiconductor reinforces our strategy to support programmable devices with silicon-proven and production-proven IP cores," said Simon Lau, president of Eureka Technology. "Eureka's IP cores will add to the growing library of pre-qualified offerings for the Delta39K devices, freeing designers to focus on broader design issues." IP Oasis The IP Oasis site was designed to be the primary portal for IP cores targeted at Cypress's Delta39K CPLDs. The cores will be available as optimized netlists. Located at http://www.cypress.com/pld/ipoasis, IP Oasis allows users to view and select prequalified intellectual property cores and directs visitors to the IP Vendor's site for license and download. This collaboration results in a complete CPLD solution. Cypress Delta39K Family of CPLDs Cypress's new Delta39K CPLDs offer up to 350,000 usable gates, approximately ten times the size of today's largest CPLD. The family offers more embedded memory - 240 Kbits for the 100,000-gate Delta39K100 - than any other programmable logic device, including even the largest field-programmable gate arrays (FPGAs). Delta39K is also the first programmable logic device to embed First-In First-Out (FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods. FIFO - first-in first-out ) control and dual-port memory arbitration logic into each specialty memory block. This significantly reduces the logic required, increases the system performance, and speeds the design cycle of any application utilizing FIFO or dual-port memory. Licensing and Availability Eureka IP cores for Cypress's line of high-performance CPLDs are available for licensing directly from Eureka Technology. The netlists of the available cores are validated and can be used in the Warp design tool. The first two cores will be available by the end of 2000: -- EP520 SDRAM Controller - Designed to tranfer data between industry-standard SDRAMs or PC100/133 SDRAM DIMMs of various sizes, this controller performs SDRAM read and write accesses based on user requests. It links multiple SDRAM subsystems with a user interface. -- EP525 Pipeline SDRAM Controller - A high-performance controller designed to transfer data between industry-standard SDRAMs and user interface at very high data rate. Its pipeline feature allows the user to overlap address phase with data phase of different transfers. Multiple rows in the SDRAM can be opened to eliminate Row-to-Column access delay. Other cores are scheduled to be introduced in 2001, including a DMA (1) (Digital Media Adapter) See digital media hub. (2) (Document Management Alliance) A specification that provides a common interface for accessing and searching document databases. controller, PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). host bridge, PCI bus arbiter, PCI master/target, PCI target, PowerPC bus master, PowerPC bus slave, PowerPC to PCI host bridge, and PowerPC bus arbiter. For more information on the Eureka core portfolio, please call (650)960-3800 or visit the Eureka Technology Web site (http://www.eurekatech.com) or Cypress's IP Oasis Web site (http://www.cypress.com/pld/ipoasis). For more information on Cypress CPLDs, customers can call (800)858-1810 in the U.S. or (408)943-2600, or visit http://www.cypress.com. About Cypress Cypress Semiconductor is "Driving the Communications Revolution"(TM) by providing high-performance integrated circuit solutions to fast-growing markets, including data communications, telecommunications, computation, consumer products, and industrial control. With a focus on emerging communications applications, Cypress's product portfolios include networking-optimized and micropower static RAMs; high-bandwidth multi-port and FIFO memories; high-density programmable logic devices; timing technology for PCs and other digital systems; and controllers for Universal Serial Bus See USB. (hardware, standard) Universal Serial Bus - (USB) An external peripheral interface standard for communication between a computer and external peripherals over an inexpensive cable using biserial transmission. (USB USB in full Universal Serial Bus Type of serial bus that allows peripheral devices (disks, modems, printers, digitizers, data gloves, etc.) to be easily connected to a computer. ). Its shares are listed on the New York Stock Exchange New York Stock Exchange (NYSE) World's largest marketplace for securities. The exchange began as an informal meeting of 24 men in 1792 on what is now Wall Street in New York City. under the symbol CY. More information about Cypress is accessible electronically on the company's worldwide Web site at http://www.cypress.com or by CD-ROM CD-ROM: see compact disc. CD-ROM in full compact disc read-only memory Type of computer storage medium that is read optically (e.g., by a laser). (call 1-800-858-1810). An electronic investor forum, and other investor information, is located at http://www.cypress.com/investor/index.html. "Safe Harbor Safe Harbor 1. A legal provision to reduce or eliminate liability as long as good faith is demonstrated. 2. A form of shark repellent implemented by a target company acquiring a business that is so poorly regulated that the target itself is less attractive. " Statement under the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and of 1995: Statements herein that are not historical facts are "forward-looking statements" involving risks and uncertainties, including by not limited to: the effect of global economic conditions, shifts in supply and demand, market acceptance, the impact of competitive products and pricing, product development, commercialization and technological difficulties, and capacity and supply constraints. Please refer to Cypress's Securities and Exchange Commission filings for a discussion of such risks. About Eureka Technology Eureka Technology is a leading intellectual property (IP) provider for PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user. and ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. designers. The company offers a wide range of silicon-proved system core logic functions and peripheral functions for systems based on PCI bus, PowerPC, ARM, or SH2-4 CPUs. These IP cores are designed to improve the design time-to-market delay, eliminate design risks, and reduce development costs. Founded in 1993, the company has a strong customer base in the United States, Japan and Europe. For more information about the company, please visit the Web site at http://www.eurekatech.com or send email to info@eurekatech.com. Delta39K, Warp and"Driving the Communications Revolution" are trademarks of Cypress Semiconductor. |
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