CynApps Takes Hardware Design to Higher Level; Chronologic Vets' EDA Startup Unveils Innovative Approach Using C++ Class Libraries at DAC.

NEW ORLEANS--(BUSINESS WIRE)--June 21, 1999--

EDA startup CynApps today announced new design methodologies and product support to raise the level of abstraction available to the hardware designer by creating a hardware description environment in C and C++. The CynApps approach is centered around Cynlib, a C++ class library for hardware description, simulation, and synthesis. The company will release more information on products, which support design entry, simulation, co-verification, and conversion to Verilog later this year.

"Higher-level design has been an unrealized goal since the adoption of RTL-based logic synthesis," stated John Sanguinetti, president of CynApps. "Neither Verilog nor VHDL are adequate and attempts to create new languages have not been successful, but using C++ we can extend C into the hardware design realm. This provides a continuum of descriptive capability from algorithmic level all the way down to RTL."

Cynlib provides the foundation for hardware design using the C language. The Cynlib classes allow the hardware designer to express design intent in a way that can be both simulated accurately and synthesized using the proven RTL-based design methodology. Both the target logic and the system environment can be written in C++ using the Cynlib classes, making it especially well-suited to system-on-chip designs. The design process can proceed from algorithm all the way to RTL in a series of small steps, always simulatable and always using the same test environment. This process of successive elaboration eliminates the common practice of rewriting a complete architectural model in RTL Verilog or VHDL.

Upcoming CynApps products will enable hardware architects and designers to use their familiar C environment for the initial design activities, bridging the gap to standard RTL synthesis and back-end tools. This approach will incorporate proven design practices and existing CAD flows with powerful object-oriented capabilities provided through standard C++ compilers.

"In our previous experience with Chronologic Simulation, we became convinced that higher-level design was essential, but the existing hardware description languages did not offer much capability," said Dr. Sanguinetti. "C is clearly the best choice for higher-level algorithmic description, but without some enhancements, you cannot express a great deal of the design information required to create effective hardware. We can provide the needed descriptive power by using C++ classes, effectively giving us an HDL dialect of C."

CynApps was founded in 1998 by Dr. John Sanguinetti, the founder of Chronologic Simulation (now part of Synopsys (NASDAQ: SNPS)), Dr. J. Randy Allen, noted compiler expert and former vice-president of engineering at Chronologic Simulation, and Andy Goodrich, graphics expert and former chief technology officer at IXmicro. The company has backing from noted technologists Gordon Bell, Andy Bechtolsheim, and Jon Rubenstein, as well as U.S. Venture Partners. CynApps is located in Santa Clara, California and can be reached at 408-588-4000, on the web at www.cynapps.com, or at DAC Booth 2957.

Note: CynApps and Cynlib are trademarks of CynApps. Verilog is a trademark of Cadence Design Systems, Inc. (NYSE: CDN)